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| 型号： | MPC603RVG200LC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 15/31页 |
| 文件大小： | 0K |
| 描述： | MPU RISC PID7V-603E 255FCCBGA |
| 标准包装： | 60 |
| 系列： | MPC6xx |
| 处理器类型： | 32-位 MPC603e PowerPC |
| 速度： | 200MHz |
| 电压： | 2.5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 255-BCBGA 裸露焊盘，255-FCCBGA |
| 供应商设备封装： | 255-FCCBGA（21x21） |
| 包装： | 托盘 |
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PID7t-603e Hardware Specifications, Rev. 5
22
Freescale Semiconductor
System Design Information
using a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to
the AVdd pin to ensure it filters out as much noise as possible. The 0.1 F capacitor should be closest to
the AVdd pin, followed by the 10 F capacitor, and finally the 10 resistor to Vdd. These traces should be
kept short and direct.
Figure 13. PLL Power Supply Filter Circuit
8.3
Decoupling Recommendations
Due to the 603e’s dynamic power management feature, large address, data buses, and high-operating
frequencies, it can generate transient power surges and high-frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the 603e system. It requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer places at least one decoupling capacitor at each Vdd and OVdd pin
of the 603e. It is also recommended that these decoupling capacitors receive their power from separate
Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10
F to provide both high- and low-frequency
filtering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values
for the Vdd pins are: 220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the
OVdd pins are: 0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT capacitors should
be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response
time necessary. They should also be connected to the power and ground planes through two vias to
minimize inductance. Suggested bulk capacitors—100 F (AVX TPS tantalum) or 330 F (AVX TPS
tantalum).
8.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be
made to all external Vdd, OVdd, and GND pins of the 603e.
Vdd
AVdd
10
10 F
0
.1 F
GND
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