- 您现在的位置：买卖IC网 > PDF目录4054 > MPC603RVG200LC (Freescale Semiconductor)MPU RISC PID7V-603E 255FCCBGA PDF资料下载
参数资料
| 型号： | MPC603RVG200LC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 30/31页 |
| 文件大小： | 0K |
| 描述： | MPU RISC PID7V-603E 255FCCBGA |
| 标准包装： | 60 |
| 系列： | MPC6xx |
| 处理器类型： | 32-位 MPC603e PowerPC |
| 速度： | 200MHz |
| 电压： | 2.5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 255-BCBGA 裸露焊盘，255-FCCBGA |
| 供应商设备封装： | 255-FCCBGA（21x21） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页当前第30页第31页
PID7t-603e Hardware Specifications, Rev. 5
8
Freescale Semiconductor
Electrical and Thermal Characteristics
This figure provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
4.2.2
Input AC Specifications
This table provides the input AC timing specifications for the PID7t-603e as defined in Figure 2 and
SYSCLK jitter
—
±150
—
±150
—
±150
—
±150
ps
4
PID7t internal PLL-relock time
—
100
—
100
—
100
—
100
s3, 5
Note:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0–3] signal description in Section 8, “System Design Information,” for valid
PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term combined) must be under
±150 ps to guarantee the input/output timing of Section 4.2.2, “Input AC Specifications,” and Section 4.2.3, “Output AC
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum time required
for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset sequence. This specification
also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must
be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100
s) during the power-on reset sequence.
6. Operation below 150 MHz is supported only by PLL_CFG[0–3] = 0b0101. Refer to Section 8.1, “PLL Configuration” for
additional information.
Table 7. Clock AC Timing Specifications (continued)
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 Tj 105 °C
Num
Characteristic
200 MHz
PBGA
200 MHz
CBGA
266 MHz
CBGA
300 MHz
CBGA
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
VM
CVil
CVih
SYSCLK
2
3
4
VM = Midpoint Voltage (1.4 V)
4
1
VM
相关PDF资料 |
PDF描述 |
|---|---|
| IDT7006S35J8 | IC SRAM 128KBIT 35NS 68PLCC |
| XF2J-1824-11A | CONN FPC 18POS 0.5MM PITCH SMD |
| IDT7006S25J8 | IC SRAM 128KBIT 25NS 68PLCC |
| IDT7006S20J8 | IC SRAM 128KBIT 20NS 68PLCC |
| MPC862PZQ80B | IC MPU PWRQUICC 80MHZ 357-PBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC603RVG300LC | 功能描述:微处理器 - MPU 603R REV2.1 HIP3 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC603RZT200LC | 功能描述:微处理器 - MPU 603E 255PBGA RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC604E | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:PowerPC 604e-TM RISC Microprocessor Technical Summary |
| MPC6071 | 制造商:International Rectifier 功能描述: |
| MPC616 | 制造商:Hammond Manufacturing 功能描述:6" X 16" MAGNET PANEL COVER |
发布紧急采购，3分钟左右您将得到回复。