参数资料
型号: MPC603RVG200LC
厂商: Freescale Semiconductor
文件页数: 23/31页
文件大小: 0K
描述: MPU RISC PID7V-603E 255FCCBGA
标准包装: 60
系列: MPC6xx
处理器类型: 32-位 MPC603e PowerPC
速度: 200MHz
电压: 2.5V
安装类型: 表面贴装
封装/外壳: 255-BCBGA 裸露焊盘,255-FCCBGA
供应商设备封装: 255-FCCBGA(21x21)
包装: 托盘
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
3
Features
and operates coherently in systems that contain four-state caches. The 603e supports single-beat and burst
data transfers for memory accesses, and supports memory-mapped I/O.
The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface
compatibility with TTL devices. The PID7t-603e is offered in both PBGA and CBGA packages. The
CBGA package supports speed bins of 200, 266, and 300 MHz. The PBGA package is a pin-compatible
drop in replacement for the CBGA; however, this package only supports speeds up to 200 MHz.
2Features
This section summarizes features of the 603e’s implementation of the PowerPC architecture. Major
features of the 603e are as follows:
High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations
Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
integer add/compare instructions
— 32 GPRs for integer operands
— 32 FPRs for single- or double-precision operands
High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte data cache—four-way, set-associative physically addressed; LRU replacement
algorithm
— 16-Kbyte instruction cache—four-way, set-associative physically addressed; LRU
replacement algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
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