参数资料
型号: MT46H128M32L4MA-54:A
元件分类: DRAM
英文描述: 128M X 32 DDR DRAM, 5 ns, PBGA168
封装: 12 X 12 MM, GREEN, PLASTIC, WFBGA-168
文件页数: 102/106页
文件大小: 3431K
Figure 54: Bank Read – Without Auto Precharge
CK
CK#
CKE
A10
BA0, BA1
tCK
tCH
tCL
tIS tIH
Row
tRCD
tRAS6
tRC
tRP
CL = 2
DM
T0
T1
T2
T3
T4
T5
T5n
T6n
T6
T7
T8
DQ7,8
DQS7
Case 1: tAC (MIN) and tDQSCK (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
DQ7,8
DQS7
tHZ (MAX)
NOP1
Command
ACTIVE
Row
Col n
READ2
Bank x
Row
Bank x
ACTIVE
Bank x
NOP1
Don’t Care
Transitioning Data
Address
PRE3
Bank x5
tRPRE
tAC (MAX)
All banks
One bank
DOUT
n
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
n
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
tLZ (MIN)
tDQSCK (MIN)
tAC (MIN)
tRPST
tDQSCK (MAX)
Note 4
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T5 is “Don’t Care” if A10 is HIGH at T5.
6. The PRECHARGE command can only be applied at T5 if tRAS (MIN) is met.
7. Refer to Figure 38 (page 77) and Figure 39 (page 78) for DQS and DQ timing details.
8. DOUTn = data out from column n.
2Gb: x16, x32 Mobile LPDDR SDRAM
Auto Precharge
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
95
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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