参数资料
型号: MT46H128M32L4MA-54:A
元件分类: DRAM
英文描述: 128M X 32 DDR DRAM, 5 ns, PBGA168
封装: 12 X 12 MM, GREEN, PLASTIC, WFBGA-168
文件页数: 92/106页
文件大小: 3431K
Figure 47: WRITE-to-READ – Uninterrupting
tDQSSnom
CK
CK#
Command1
WRITE2,3
NOP
READ
NOP
Address
Bank a,
Col b
Bank a,
Col n
NOP
T0
T1
T2
T3
T2n
T4
T5
T1n
T6
T6n
tWTR4
CL = 2
DQ5
DQS
DM
tDQSS
tDQSSmin
CL = 2
DQ5
DQS
DM
tDQSS
tDQSSmax
CL = 2
DQ5
DQS
DM
tDQSS
Don’t Care
Transitioning Data
T5n
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
Notes: 1. The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case tWTR is not required and the
READ command could be applied earlier.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. DINb = data-in for column b; DOUTn = data-out for column n.
2Gb: x16, x32 Mobile LPDDR SDRAM
WRITE Operation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
86
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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MT46H128M32LFCM-5AT:A 128M X 32 DDR DRAM, 5 ns, PBGA90
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