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参数资料
| 型号： | MT46H128M32L4MA-54:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, WFBGA-168 |
| 文件页数： | 70/106页 |
| 文件大小： | 3431K |
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Status Read Register
The status read register (SRR) is used to read the manufacturer ID, revision ID, refresh
multiplier, width type, and density of the device, as shown in Figure 30 (page 67). The
SRR is read via the LOAD MODE REGISTER command with BA0 = 1 and BA1 = 0. The
sequence to perform an SRR command is as follows:
1. The device must be properly initialized and in the idle or all banks precharged state.
2. Issue a LOAD MODE REGISTER command with BA[1:0] = 01 and all address pins
set to 0.
3. Wait tSRR; only NOP or DESELECT commands are supported during the tSRR time.
4. Issue a READ command.
5. Subsequent commands to the device must be issued tSRC after the SRR READ com-
mand is issued; only NOP or DESELECT commands are supported during tSRC.
SRR output is read with a burst length of 2. SRR data is driven to the outputs on the first
bit of the burst, with the output being “Don’t Care” on the second bit of the burst.
Figure 29: Status Read Register Timing
Command
BA0, BA1
CK
CK#
Address
READ
NOP
T0
T1
T2
T3
T4
T5
T6
Don’t Care
NOP
DQS
DQ
SRR
out4
tRP
tSRR
tSRC
PRE1
LMR
NOP2
NOP
Valid
T8
BA0 = 1
BA1 = 0
0
Note 5
CL = 33
Transitioning Data
Notes: 1. All banks must be idle prior to status register read.
2. NOP or DESELECT commands are required between the LMR and READ commands
(tSRR), and between the READ and the next VALID command (tSRC).
3. CAS latency is predetermined by the programming of the mode register. CL = 3 is shown
as an example only.
4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register.
5. The second bit of the data-out burst is a “Don’t Care.”
2Gb: x16, x32 Mobile LPDDR SDRAM
Status Read Register
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
66
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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| MT46H128M32LFCM-5AT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
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| MT46V128M4FN-75E:C | 128M X 4 DDR DRAM, 0.75 ns, PBGA60 |
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相关代理商/技术参数 |
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| MT46H16M16 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Mobile Double Data Rate (DDR) SDRAM |
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