参数资料
型号: MT46H128M32L4MA-54:A
元件分类: DRAM
英文描述: 128M X 32 DDR DRAM, 5 ns, PBGA168
封装: 12 X 12 MM, GREEN, PLASTIC, WFBGA-168
文件页数: 93/106页
文件大小: 3431K
Figure 48: WRITE-to-READ – Interrupting
tDQSS (NOM)
CK
CK#
Command
WRITE1,2
NOP
Address
Bank a,
Col b
Bank a,
Col n
READ
T0
T1
T2
T3
T2n
T4
T5
T5n
T1n
T6
T6n
CL = 3
DQ5
DQS4
DM
tDQSS (MIN)
CL = 3
DQ5
DQS4
DM
tDQSS (MAX)
CL = 3
DQ5
DQS4
DM
Don’t Care
Transitioning Data
tDQSS
DIN
b+1
DIN
b
DIN
b+1
DIN
b
DIN
b+1
DIN
b
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
DOUT
n
DOUT
n + 1
tWTR3
Notes: 1. An interrupted burst of 4 is shown; 2 data elements are written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. tWTR is referenced from the first positive CK edge after the last data-in pair.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. DINb = data-in for column b; DOUTn = data-out for column n.
2Gb: x16, x32 Mobile LPDDR SDRAM
WRITE Operation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
87
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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