参数资料
型号: MT46H128M32L4MA-54:A
元件分类: DRAM
英文描述: 128M X 32 DDR DRAM, 5 ns, PBGA168
封装: 12 X 12 MM, GREEN, PLASTIC, WFBGA-168
文件页数: 83/106页
文件大小: 3431K
Figure 39: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32)
DQ (Last data valid)4
DQ4
DQS0/DQS1/DQS2/DQS3
DQ (Last data valid)
DQ (First data no longer valid)
DQ (First data no longer valid)4
DQ and DQS, collectively6,7
CK
CK#
Byte
0
Byte
1
Byte
2
Byte
3
Data valid
window
Data valid
window
Data valid
window
Data valid
window
T1
T2
T2n
T3
T3n
T4
tHP1
tDQSQ2,3
T2
T2n
T3
T3n
T2
T2n
T3
T3n
T2
T2n
T3
T3n
tQH5
tHP1
tQH5
Notes: 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
2. DQ transitioning after DQS transitions define the tDQSQ window.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time; it begins with
DQS transition and ends with the last valid DQ transition.
4. Byte 0 is DQ[7:0], byte 1 is DQ[15:8], byte 2 is DQ[23:16], byte 3 is DQ[31:24].
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for
byte 2; DQ[31:23] and DQS3 for byte 3.
2Gb: x16, x32 Mobile LPDDR SDRAM
READ Operation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
78
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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