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参数资料
型号： MT48LC2M32LFFC
厂商： Micron Technology, Inc.
英文描述： 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4组同步动态RAM)
中文描述： 为512k × 32 × 4银行3.3V的内存电压（3.3V，512K采样× 32 × 4组同步动态RAM）的
文件页数： 1/50页
文件大小： 1054K
代理商： MT48LC2M32LFFC
1
64Mb: x32, 3.3V SDRAM
BatRam_3V.p65 – Rev. 0.7, Pub. 2/01
2001, Micron Technology, Inc.
64Mb: x32, 3.3V
SDRAM
PRELIMINARY
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
SYNCHRONOUS
DRAM
MT48LC2M32LFFC - 512K x 32 x 4 banks
www.micron.com/products/datasheets/sdramds.html
FEATURES
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge and Auto Refresh Modes
Self Refresh Mode
4,096-cycle standard refresh
LVTTL-compatible inputs and outputs;
Single power supply: 3.3V
V
DD
Q 3.3V
CAS Latency of 1, 2, or 3
Temperature Compensated Self Refresh
Fully synchronous; all signals registered on posi-
tive edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
OPTIONS
Configurations
2 Meg x 32 (512K x 32 x 4 banks)
WRITE Recovery (
t
WR/
t
DPL)
t
WR = 1 CLK - to 60 MHz
with Manual Precharge
Plastic Package - OCPL*
90-Ball FBGA
Timing (Cycle Time)
8ns (125 MHz)
10ns (100 MHz)
L
None
FC
-8
-10
Part Number Example:
MT48LC2M32LFFC
KEY TIMING PARAMETERS
SPEED
GRADE
CLOCK
FREQUENCY CL = 2** CL = 3**
ACCESS TIME
SETUP
TIME
HOLD
TIME
-8
-10
-8
-10
125 MHz
100 MHz
100 MHz
83 MHz
–
–
7ns
7ns
–
–
2ns
2ns
2ns
2ns
1ns
1ns
1ns
1ns
8ns
8ns
*Off-center parting line
**CL = CAS (READ) latency
64Mb SDRAM PART NUMBER
PART NUMBER
MT48LC2M32LFFC
ARCHITECTURE
2 Meg x 32
PIN ASSIGNMENT (Top View)
90-Ball FBGA
Note:
The # symbol indicates signal is active LOW.
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0–A10)
4 (BA0, BA1)
256 (A0–A7)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
1
2
3
4
6
7
8
9
5
DQ26
DQ28
V
SS
Q
V
SS
Q
V
DD
Q
V
SS
A4
A7
CLK
DQM1
V
DD
Q
V
SS
V
SS
Q
DQ11
DQ13
DQ24
V
DD
Q
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
V
DD
Q
DQ15
V
SS
V
SS
Q
DQ25
DQ30
NC
A3
A6
NC
A9
NC
V
SS
DQ9
DQ14
V
SS
Q
V
SS
V
DD
V
DD
Q
DQ22
DQ17
NC
A2
A10
NC/
A12
BA0
CAS#
V
DD
DQ6
DQ1
V
DD
Q
V
DD
DQ21
DQ19
V
DD
Q
V
DD
Q
V
SS
Q
V
DD
A1
NC/
A11
RAS#
DQM0
V
SS
Q
V
DD
Q
V
DD
Q
DQ4
DQ2
DQ23
V
SS
Q
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS#
WE#
DQ7
DQ5
DQ3
V
SS
Q
DQ0
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
Preliminary Ball and Array
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