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参数资料
| 型号： | MT48LC2M32LFFC |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4组同步动态RAM) |
| 中文描述： | 为512k × 32 × 4银行3.3V的内存电压（3.3V，512K采样× 32 × 4组同步动态RAM）的 |
| 文件页数： | 34/50页 |
| 文件大小： | 1054K |
| 代理商： | MT48LC2M32LFFC |
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34
64Mb: x32, 3.3V SDRAM
BatRam_3V.p65 – Rev. 0.7, Pub. 2/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32, 3.3V
SDRAM
PRELIMINARY
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
DD
, V
DD
Q = 3.3V;
f = 1 MHz, T
A
= 25oC; pin under test biased at
1.3V.
3.
I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with
minimum cycle time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation
over the temperature range is ensured, provided
the mode register is correct for the temperature.
6.
An initial pause of 100μs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
DD
and V
DD
Q must be powered up simultaneously.
V
SS
and V
SS
Q must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the
t
REF refresh requirement
is exceeded.
7.
AC characteristics assume
t
T = 1ns.
8.
In addition to meeting the transition rate
specification, the clock and CKE must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in a
monotonic manner.
9.
Outputs measured at 0.5*V
DD
Q with equivalent
load of 30pf:
Q
30pF
10.
t
HZ defines the time at which the output
achieves the open circuit condition; it is not a
reference to V
OH
or V
OL
. The last valid data
element will meet
t
OH before going High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V,
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at V
IL
(MAX) and V
IH
(MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no
more than once in any 20ns (-8) period and are
otherwise at valid V
IH
or V
IL
levels.
13. I
CC
specifications are tested after the device is
properly initialized.
14. Timing actually specified by
t
CKS; clock(s)
specified as a reference only at minimum cycle
rate.
15. Timing actually specified by
t
WR plus
t
RP;
clock(s) specified as a reference only at minimum
cycle rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing
parameter.
18. The I
DD
current will decrease as the CAS latency is
reduced. This is due to the fact that the maxi-
mum cycle rate is slower as the CAS latency is
reduced.
19. Address transitions average one transition every
20ns.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on
t
CK = 10ns for -8
22. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 0.45V
DD
for a
pulse width
￡
3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -0.45V
DD
V for a pulse
width
￡
3ns, and the pulse width cannot be
greater than one third of the cycle rate.
23. The clock frequency must remain constant
during access or precharge states (READ, WRITE,
including
t
WR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (
t
RP) begins xns after the first clock delay,
after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. Check factory for availability of specially
screened devices having
t
WQ = 10ns.
t
WR = 1
t
CK
for 100 MHz and slower (
t
CK = 10ns and higher)
in manual precharge.
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