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参数资料
| 型号： | MT48LC2M32LFFC |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4组同步动态RAM) |
| 中文描述： | 为512k × 32 × 4银行3.3V的内存电压（3.3V，512K采样× 32 × 4组同步动态RAM）的 |
| 文件页数： | 7/50页 |
| 文件大小： | 1054K |
| 代理商： | MT48LC2M32LFFC |
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7
64Mb: x32, 3.3V SDRAM
BatRam_3V.p65 – Rev. 0.7, Pub. 2/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
64Mb: x32, 3.3V
SDRAM
PRELIMINARY
NOTE:
1. For a burst length of two, A1–A7 select the block-of-two
burst; A0 selects the starting column within the block.
2. For a burst length of four, A2–A7 select the block-of-four
burst; A0–A1 select the starting column within the block.
3. For a burst length of eight, A3–A7 select the block-of-eight
burst; A0–A2 select the starting column within the block.
4. For a full-page burst, the full row is selected and
A0–A7 select the starting column.
5. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the
block.
6. For a burst length of one, A0–A7 select the unique column
to be accessed, and Mode Register bit M3 is ignored.
Table 1
Burst Definition
Burst
Length
Starting Column
Address:
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
A 0
2
0
0-1
0-1
1
1-0
1-0
A 1
A 0
0
0
0-1-2-3
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A 2
A 1
A 0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n = A0–A7
Cn, Cn + 1, Cn + 2
Page
Cn + 3, Cn + 4...
Not Supported
(256)
(Location 0 -256)
…Cn - 1,
Cn…
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A10
A11
A12
10
11
12
Res.*
*Should program
M9, M10 = “0, 0”
to ensure compatibility
with future devices.
NOTE:
1. Temperature ranges will change
and the mode register setting is
moving to an extended mode
register in next generation parts
to comply with standards. Call
factory if you plan on using this
feature.
Self Refresh
Freq. Level
M12
M11
Self Refresh
1
0
0
+25oC – +60oC
0
1
+70oC – +85oC
1
0
-40oC – +25oC
Figure 1
Mode Register Definition
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.
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