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参数资料
| 型号： | MT49H16M16FM |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | REDUCED LATENCY DRAM RLDRAM |
| 中文描述： | 低延迟DRAM延迟DRAM |
| 文件页数： | 13/43页 |
| 文件大小： | 652K |
| 代理商： | MT49H16M16FM |
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13
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q, RLDRAM
ter upon power-up or whenever the TAP controller is
given a test logic reset state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and bi-
directional pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock
can only operate at a frequency up to 10 MHz, while the
RLDRAM clock operates more than an order of magnitude
faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The TAP
may then try to capture a signal while in transition (meta-
stable state). This will not harm the device, but there is no
guarantee as to the value that will be captured. Repeat-
able results may not be possible.
To guarantee that the boundary scan register will
capture the correct value of a signal, the RLDRAM signal
must be stabilized long enough to meet the TAP controller’s
capture setup plus hold time (
t
CS plus
t
CH). The RLDRAM
clock input might not be captured correctly if there is no
way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan
register.
Once the data is captured, it is possible to shift out the
data by putting the TAP into the Shift-DR state. This places
the boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is
not implemented, putting the TAP to the Update-DR state
while performing a SAMPLE/PRELOAD instruction will
have the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruc-
tion register and the TAP is placed in a Shift-DR state, the
bypass register is placed between TDI and TDO. The
advantage of the BYPASS instruction is that it shortens
the boundary scan path when multiple devices are con-
nected together on a board.
RESERVED
These instructions are not implemented but are re-
served for future use. Do not use these instructions.
IDENTIFICATION (ID) REGISTER
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
command is loaded in the instruction register. The IDCODE
is hardwired into the RLDRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has a vendor code and other information described in the
Identification Register Definitions table.
TAP INSTRUCTION SET
OVERVIEW
Eight different instructions are possible with the three-
bit instruction register. All combinations are listed in the
Instruction Codes table (see page 16). Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
The TAP controller used in this RLDRAM is not fully
compliant to the 1149.1 convention because some of the
mandatory 1149.1 instructions are not fully implemented.
The TAP controller cannot be used to load address, data
or control signals into the RLDRAM and cannot preload
the I/O buffers. The RLDRAM does not implement the
1149.1 commands EXTEST or INTEST or the PRELOAD
portion of SAMPLE/PRELOAD; rather it performs a cap-
ture of the I/O ring when these instructions are executed.
Instructions are loaded into the TAP controller during
the Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI
and TDO pins. To execute the instruction once it is shifted
in, the TAP controller needs to be moved into the Update-
IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to
be executed whenever the instruction register is loaded
with all 0s. EXTEST is not implemented in the TAP
controller, hence this device is not IEEE 1149.1 compli-
ant.
The TAP controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the RLDRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. EXTEST does not place the
RLDRAM outputs in a High-Z state, CQ, CQ#.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-
bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction regis-
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