参数资料
型号: MT49H16M16FM
厂商: Micron Technology, Inc.
英文描述: REDUCED LATENCY DRAM RLDRAM
中文描述: 低延迟DRAM延迟DRAM
文件页数: 4/43页
文件大小: 652K
代理商: MT49H16M16FM
4
256: x16, x32 RLDRAM
MT49H8M32_3.p65 – Rev. 3, Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
ADVANCE
256Mb: x16, x32
2.5V V
EXT
, 1.8V V
DD
, 1.8V V
DD
Q, RLDRAM
TABLE OF CONTENTS
General Description .......................................................
Power-Up Initialization ...................................................
Functional Block Diagram, 8 Meg x 32................
Power-Down ...................................................................
Functional Block Diagram, 16 Meg x 16 .............
8 Meg x 32 Ball Assignment (Top View)
144-Ball T-FBGA ...............................................
16 Meg x 16 PIN Assignment (Top View)
144-Ball T-FBGA ...............................................
Ball Descriptions ....................................................
Ball Descriptions (continued)................................
Truth Table 1 ..........................................................
Programming Description..............................................
RLDRAM Programming Table ..............................
Mode Register Description ............................................ 10
Mode Register Command Table........................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) ................ 11
Disabling the JTAG Feature .......................................... 11
Figure 1, TAP Controller State Diagram .............. 11
Test Access Port (TAP).................................................. 11
Test Clock (TCK)........................................................ 11
Test MODE SELECT (TMS)...................................... 11
Test Data-In (TDI) ...................................................... 11
Test Data-Out (TDO) ................................................. 12
Performing a TAP Reset ........................................... 12
TAP Registers ............................................................ 12
Instruction Register.................................................... 12
Figure 2, TAP Controller Block Diagram ............. 12
Bypass Register ......................................................... 12
Boundary Scan Register ........................................... 12
Identification (ID) Register ........................................ 13
TAP Instruction Set ........................................................ 13
Overview ..................................................................... 13
Extest .......................................................................... 13
Idcode ......................................................................... 13
Sample Z .................................................................... 13
Sample/Preload ......................................................... 13
Bypass ........................................................................ 14
TAP Timing ............................................................. 14
TAP AC Electrical Characteristics ........................ 14
Reserved .................................................................... 14
TAP DC Electrical Characteristics and
Operating Conditions ........................................ 15
Identification Register Definitions ........................ 16
Scan Register Sizes .............................................. 16
Instruction codes ................................................... 16
Boundary Scan (Exit) Order ................................. 17
1
1
2
2
3
5
5
6
7
8
9
9
Absolute Maximum Ratings .......................................... 18
Recommended DC Operation Ranges ........................ 18
DC Electrical Characteristics and
Operating Conditions ........................................ 18
DC Electrical Characteristics and
Operating Conditions ........................................ 19
I
DD
Electrical Characteristics and
Operating Conditions ........................................ 20
Capacitance ........................................................... 21
AC Electrical Characteristics and
Operating Conditions ........................................ 21
AC Electrical Characteristics ................................ 22
Timing Waveforms
General Overview and Timing Definition
(BL2/WL2).......................................................... 23
READ Timing (BL = 2)........................................... 24
READ Timing (BL = 4)........................................... 25
WRITE Timing (BL = 2, RL = 6) ........................... 26
WRITE Timing (BL = 4, RL = 6) ........................... 27
READ to WRITE Timing (BL = 2, WL = 2) .......... 28
WRITE to READ Timing (BL = 2, WL = 2) .......... 29
Refresh Timing....................................................... 30
Example of Refresh Implementation
(Cyclic Bank Burst Refresh) ............................. 31
WRITE Data Mask Timing (BL = 2, WL = 2) ....... 32
WRITE Data Mask Timing (BL = 4, WL = 1) ....... 33
WRITE/READ and READ/WRITE Timing, Cyclic
Bank Access (RL = 6, BL = 2, WL = 3) ........... 34
WRITE/READ and READ/WRITE Timing, Cyclic
Bank Access (RL = 5, BL = 2, WL = 2) ........... 35
WRITE/READ and READ/WRITE Timing, Cyclic
Bank Access (RL = 6, BL = 4, WL = 2) ........... 36
WRITE/READ and READ/WRITE Timing, Cyclic
Bank Access (RL = 5, BL = 4, WL = 1) ........... 37
Random Access, Single Bank
(RL = 6, BL = 2, WL = 3)................................... 38
Random Access, Single Bank
(RL = 5, BL = 2, WL = 2,
t
RC = 6).................... 39
Random Access, Single Bank
(RL = 6, BL = 4, WL = 2)................................... 40
Random Access, Single Bank
(RL = 5, BL = 4, WL = 1,
t
RC = 6).................... 41
Package Drawing
144-Ball T-FBGA .................................................... 42
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