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参数资料
| 型号： | MT8952BPR |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 13/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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MT8952B
Data Sheet
20
Zarlink Semiconductor Inc.
Primary End of the Link
The MT8952B is operating in the internal timing mode with the C-channel transceiver action enabled. The
processor loads the data or control information (D Channel) in the transmit FIFO which is packetized in HDLC
format and shifted out serially during the selected channels of the outgoing ST-BUS (CDSTo). The channels and
the number of bits per frame (frame period=125
sec) can be selected by TC0-TC3 bits in the Timing Control
Register. Since channel 1 is reserved for the C-channel information and channels 2 and 3 carry B-channels (64
kbps each), the D-channel information can only be sent on channel-0. Similarly the incoming packets on CDSTi are
loaded into receive FIFO after the removal of all overhead bits and checked for any errors. The microprocessor will
then read the data from the receive FIFO.
The DNIC (MT8972) is selected to operate in single port, master mode with the digital network (DN) option enabled.
The B-channels, B1 and B2, are shown connected directly to the DNIC. Hence, these should be in ST-BUS format
enabled at the appropriate timeslot (channels 2 and 3). It can be the outputs of voice codecs (MT896X) providing
voice communication or data codecs (MT8950) for communication between RS232-C type terminals. It is possible
to use the HDLC protocol on B1 and B2 channels to provide the error detection.
This can be done by using a separate MT8952B enabled appropriately to shift out the formatted data during
channels 2 and 3 or by multiplexing the same MT8952B between B- and D- channels.
Secondary End of the Link
At the secondary end of the communication link, a similar procedure is adopted to transmit/receive the data and
control information.
The MT8952B operates in the Internal Timing Mode as at the primary end, but the DNIC (MT8972) is selected to
operate in single port, slave mode with the digital network capability enabled.
The other functions and procedures are similar to those at the primary end.
The timing signals like CKi (C2i or C4i) and F0i are provided externally at the primary end and at the secondary
end, they are derived from the received data.
Although this application describes the communication
between two
stations
over
a dedicated link, it can
be modified to serve a switched communication path by additional control functions and a call set-up procedure
many of which can be achieved in software.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT8952BPR1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel |
| MT8952BS | 制造商:Microsemi Corporation 功能描述: |
| MT8952BS1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC PROTOCOL CONTROLLER - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC PROTOCOL CONTROLLER |
| MT8960 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Integrated PCM Filter Codec |
| MT8960AE | 制造商:ZARLINK 功能描述: |
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