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参数资料
| 型号： | MT8952BPR |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 7/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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MT8952B
Data Sheet
15
Zarlink Semiconductor Inc.
Transmit FIFO Full
When the Transmit FIFO is full, this state is indicated by the Transmit FIFO status bits in the FIFO Status Register.
These bits do not change state for two bit periods after an access of the FIFO from either the serial port or the
microprocessor port. The bit period is determined by the CKi signal frequency. If the bus cycle of the controlling
microprocessor is much shorter than the bit period, the Transmit FIFO status bits may not be updated in time for the
next microprocessor read of the FIFO Status Register.
To make sure that the microprocessor does not overwrite the Tx FIFO, if over four bytes of information have been
written to the Tx FIFO, the microprocessor should wait for a 4/19 FULL interrupt before writing to the Tx FIFO again.
When a 4/19 FULL interrupt has been received, a maximum of 15 bytes should be written to the Tx FIFO, then
transfer of information to the Tx FIFO should stop and the 4/19 FULL interrupt should be waited for once more. The
FIFO may be allowed to empty if no more information is to be sent at the moment. This procedure should keep
software independent of the frequency of the CKi signal.
Transmit Underrun
A transmit underrun occurs when the last byte loaded into the transmit FIFO was not ‘flagged’ with the ‘end of
packet’ (EOP) bit and there are no more bytes in the FIFO. In such a situation, the Protocol Controller transmits the
abort sequence (eight ONEs) and moves to the selected link channel state.
Abort Transmission
If it is desired to abort the packet currently being loaded into the transmit FIFO, the next byte written to the FIFO
should be ‘flagged’ to cause this to happen. The FA bit of the Control Register must be set HIGH, before writing the
next byte into the FIFO. This bit is cleared automatically once the byte is written to the FIFO. When the ‘flagged’
byte reaches the bottom of the FIFO, a frame abort sequence is sent instead of the byte and the transmitter
operation returns to normal.
Go Ahead Transmission
By setting the IFTF bits in the Control Register appropriately the transmitter can be made to send the Go Ahead
sequences when the Protocol Controller is not sending the packets. Since the go ahead is defined as 011111110,
contiguous 7FHex’ s appear as go aheads. As long as the IFTF bits are set to choose go aheads, the transmitter will
send them even if data is subsequently loaded into the FIFO. Only when the IFTF bits are set to select something
other than go aheads, will the data be transmitted.
C-Channel Transmission
By setting the C1EN bit in the Timing Control Register HIGH, the information loaded in the C-Channel Control
Register can be transmitted over channel-1 timeslot of the outgoing ST-BUS (CDSTo). This is available only during
the Internal Timing Mode of the Protocol Controller.
Transparent Data Transfer
The IFTF bits in the Control Register can be set to provide transparent data transfer disabling the protocol
functions. The transmitter no longer generates the Flag, GA, Abort and Idle sequences nor does it insert the zeros
and calculate the FCS. It operates in both timing modes in bytewide manner and transmits data serially on CDSTo.
If the Protocol Controller is in the Internal Timing Mode and the Timing Control bits are set to select 2, 6 or 7
bits/frame, the corresponding least significant bits of every byte loaded into the transmit FIFO are only transmitted.
The transparent data transfer facility is not available when the Timing Control bits are set for 1 bit/frame. In case the
FIFO is empty, the last byte or the portion of the last byte, written to the FIFO is transmitted repeatedly. Note that
the transparent data transfer can be disabled immediately in software (unlike during the transmission of packets)
using TxEN bit in the Control Register.
The operation of the transmitter is similar in the External Timing Mode.
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