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参数资料
| 型号： | MT8952BPR |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 28/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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MT8952B
Data Sheet
5
Zarlink Semiconductor Inc.
bit in the Control Register is HIGH, the incoming packet is recognized only if the address byte matches the byte
stored in the Receive Address Register or the address byte is the All-Call Address (all ONEs). The LSB of the
Receive Address Register is set LOW permanently and the comparison is done only on upper seven bits of the
received address byte. The address detection can be limited only to the upper six bits by setting HIGH both RA6/7
and RxAD bits in the Control Register.
Frame Check Sequence (FCS)
The 16 bits following the data field are the frame check sequence bits. The generator polynomial is:
G(x)=x16+x12+x5+1
The transmitter calculates the FCS on all bits of the data field and transmits after the data field and before the end
flag. The receiver performs a similar computation on all bits of the received data and FCS fields and the result is
compared with FOB8Hex. If it matches, the received data is assumed error free. The error status of the received
packet is indicated by D7 and D6 bits in the FIFO Status Register.
Zero Insertion and Deletion
The Protocol Controller, while sending either data from the FIFO or the 16 bits FCS, checks the transmission on a
bit-by-bit basis and inserts a ZERO after every sequence of five contiguous ONEs (including the last five bits of
FCS) to ensure that the flag sequence is not simulated. Similarly the receiver examines the incoming frame content
and discards any ZERO directly following the five contiguous ONEs.
Abort
The transmitter aborts a frame by sending eight consecutive ONEs. The FA bit in the Control Register along with a
write operation to the Transmit Data Register enables the transmission of abort sequence instead of the byte
written to the register. On the receive side, the ABRT bit in the General Status Register is set whenever an abort
sequence (7 or more continuous 1’s) is received. The abort sequence causes the receiver to abandon whatever it
was doing and start searching for a start flag. The FA bit in the Interrupt Status Register is set when an abort
sequence is received following a start flag and at least four data bytes (minimum for a valid frame).
Interframe Time Fill and Link Channel States
When the HDLC Protocol Controller is not sending packets, the transmitter can be in any of three states mentioned
below depending on the status of the IFTF0 and IFTF1 bits in the Control Register. These bits are also used to
disable the protocol function to provide the transparent parallel access to the serial bus through the microprocessor
port.
Idle State
The Idle state is defined as 15 or more contiguous ONEs. When the HDLC Protocol Controller is observing this
condition on the receiving channel, the Idle bit in the General Status Register is set HIGH. On the transmit side, the
Protocol Controller ends the Idle state when data is loaded into the transmit FIFO.
Interframe Time Fill State
The Protocol Controller transmits continuous flags (7EHex) in Interframe time fill state and ends this state when data
is loaded into the transmit FIFO.
Go Ahead State
Go Ahead is defined by the 9 bit sequence 011111110 (7FHex followed by a ZERO), and hence contiguous 7F’s
appear as Go Aheads. Once the transmitter is in ‘Go Ahead’ state, it will continue to remain so even after the data
is loaded into the FIFO. This state can only be changed by setting the IFTF bits in the Control Register to something
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相关代理商/技术参数 |
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|---|---|
| MT8952BPR1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel |
| MT8952BS | 制造商:Microsemi Corporation 功能描述: |
| MT8952BS1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC PROTOCOL CONTROLLER - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC PROTOCOL CONTROLLER |
| MT8960 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Integrated PCM Filter Codec |
| MT8960AE | 制造商:ZARLINK 功能描述: |
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