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参数资料
| 型号： | MT8952BPR |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 3/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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MT8952B
Data Sheet
11
Zarlink Semiconductor Inc.
Receive Address Register (Read/Write)
Figure 8 - Receive Address Register
The data in this register (Figure 8) defines the unique address for the HDLC Protocol Controller. If address
recognition is enabled using the RxAD and RA6/7 bits in the Control Register, an incoming packet is recognized
only if its address byte (seven or six most significant bits) matches the corresponding bits in this register or if the
address is an "all-call". The LSB of the Receiver Address Register is set LOW permanently and the address
comparison is done only on remaining bits of the register.
C-Channel Control Register (Read/Write)
Figure 9 - C-Channel Control Register
The data written to this register (Figure 9) is transmitted on channel-1 slot of the outgoing ST-BUS (CDSTo), when
enabled by C1EN bit in the Timing Control Register. This feature can only be used when the HDLC Protocol
Controller is in the Internal Timing Mode.
Timing Control Register (Read/Write)
The Timing Control Register (Figure 10) controls the timing mode and other related operations and provides a
software reset to the Protocol Controller. The various bits in this register are described below:
Figure 10 - Timing Control Register
RST - Reset: When this bit is set HIGH, all the registers in the HDLC Protocol Controller are reset and the data in
the FIFOs is lost. This is equivalent to the external reset with the exception that the RST bit does not affect itself or
the Watchdog Timer Register and WD output. The RST bit must be “cleared” (written as a logic “0”) twice before the
MT8952B will be removed from its reset state (see section on RESET operation).
IC - Internal Control: When this bit is cleared to ZERO, the Protocol Controller is in the External Timing Mode.
The transmit and receive sections are enabled by the inputs TxCEN and RxCEN respectively, and F0i is used only
for the watchdog timer operation. When this bit is a ONE, the Protocol Controller is in the Internal Timing Mode. The
transmit and receive sections are enabled by the internally generated timings derived from the inputs CKi and F0i.
The F0i input defines the beginning of a frame (Figure 24) and the transmitter and receiver sections are enabled in
the timeslots as determined by the bits TCO-TC3. The inputs TxCEN and RxCEN are ignored in this mode.
C1EN - Channel-1 Enable: When HIGH, it enables the transmission of C-channel information on channel-1 time-
slot of the outgoing ST-BUS (CDSTo) and when LOW, puts CDSTo into high impedance state during that period.
However, the C-channel information is received independently and the C-channel Status Register is updated
continuously. Note that C1EN has relevance only during the Internal Timing Mode.
BRCK- Bit Rate Clock: This bit is used during the Internal Timing Mode to select the clock rate and ignored if the
Protocol Controller is in the External Timing Mode. It should be set HIGH if the input clock (CKi) is at the bit rate
(C2i) and should be LOW for the clock input at 2 x bit rate (C4i).
In both cases, the clock should be properly
phase related to F0i as shown in Figure 25.
D7
D6
D5
D4
D3
D2
D1
D0
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
D7
D6
D5
D4
D3
D2
D1
D0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
D7
D6
D5
D4
D3
D2
D1
D0
RST
IC
C1EN BRCK
TC3
TC2
TC1
TC0
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相关代理商/技术参数 |
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|---|---|
| MT8952BPR1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel |
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