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参数资料
| 型号： | MT8952BPR |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 2/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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MT8952B
Data Sheet
10
Zarlink Semiconductor Inc.
Figure 7 - Control Register
TxEN -Transmit Enable: When set HIGH, this bit enables the transmitter and when LOW, disables it setting the
serial output (CDSTo) to high impedance state. If the transmitter is disabled during the transmission of a packet
using this bit, the Protocol Controller will wait until the completion of the packet and closing flag is transmitted or the
packet is aborted before setting the output (CDSTo) to high impedance state.
Thus TxEN
bit controls the
transmission packet by packet unlike TxCEN input (pin 1) which controls it bit-by-bit. However, if the Protocol
Controller is in transparent data transfer state, the transmission will be stopped within two bit periods (maximum)
and set the output to high impedance state.
RxEN - Receive Enable: This bit enables the receiver when set HIGH and disables it when LOW. If this bit goes
LOW during the reception of the packet, the receiver can only be disabled after the current packet and its closing
flag are received or an abort is detected. Thus RxEN bit controls the receiver section packet by packet unlike
RxCEN input (pin 2) which controls it bit-by-bit. However, if the Protocol Controller is in transparent data transfer
state, the receiver will be disabled immediately.
RxAD - Receive Address Detect: This bit when set HIGH, enables the address detection for the received packets.
This causes the receiver to recognize only those packets having a unique address as programmed in the Receive
Address Register or if the address byte is the All-Call address (all ONEs). The address comparison is done only on
seven bits (compatible to the first byte of the address field defined in LAPD-CCITT) and an All-Call is defined as all
ONEs in upper seven bits of the received address field. If RxAD is LOW, the address detection is disabled and
every valid packet is recognized.
RA6/7 - Receive Address Six/Seven bits: This bit, when set HIGH, limits the address detection only to the upper
six bits of the received address byte (last 6 bits of received address field) and when LOW, allows the address
comparison on seven bits. An "all call", in this case is defined as all ONEs in the upper six bits only. RA6/7 is
ignored if the address detection is disabled (RxAD=0).
IFTF0 and IFTF1 - Interframe Time Fill: Setting these bits according to the table below (Table 6) causes the
transmitter to be in one of the active or idle states or allows the Protocol Controller to be in the transparent data
transfer state.
Table 6 - Interframe Time Fill Bits
FA - Frame Abort: When set HIGH, this bit’tags’ the next byte written to the transmit FIFO and causes an abort
sequence (eight ONEs) to be transmitted when it reaches the bottom of the FIFO. The abort sequence will be
transmitted instead of the byte that was tagged. The FA bit is cleared to ZERO upon writing the data to the transmit
FIFO. As a result, a ‘read’ of this register bit will not reflect the last data written to it.
EOP - End Of Packet: Writing a ONE to this bit ‘tags’ the next byte written to the transmit FIFO to indicate that it is
the last data byte of the packet. This bit is cleared to ZERO upon writing the data to the transmit FIFO. As a result,
a read of this register bit will not indicate the last data written to it.
D7
D6
D5
D4
D3
D2
D1
D0
TxEN RxEN RxAD RA6/7 IFTF1 IFTF0
FA
EOP
IFTF Bits
Result
IFTF1
IFTF0
0
Idle State (All ONEs)
0
1
Interframe Time Fill state
(Continuous Flags)
1
0
Transparent Data Transfer
1
Go Ahead state (Continuous
7FHEX)
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