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参数资料
| 型号： | MT8952BPR |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 32/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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MT8952B
Data Sheet
9
Zarlink Semiconductor Inc.
Table 4 - Receive FIFO Status
Tx FIFO Status: These two bits (D3 and D2) indicate the status of transmit FIFO as shown in Table 5.
Table 5 - Transmit FIFO Status
The Tx FIFO status bits are updated in the same manner as the Rx FIFO bits, except that in external timing mode,
and in internal 2.048 Mbps timing mode, the Tx FIFO status bits are updated after two falling edges of the CKi or the
C2i signal (see the section on Transmit Operation - Normal Packets).
Receive Data Register (Read)
Reading the Receive Data Register (Figure 5) puts the first byte from the receive FIFO on the data bus. The first bit
of the data received on the serial input (CDSTi) is considered to be the LSB and is available on D0 of the data bus.
Figure 5 - Receive Data Register
Transmit Data Register (Write)
Writing to Transmit Data Register (Figure 6) puts the data present on the data bus into the transmit FIFO. The LSB
(D0) is transmitted first.
Figure 6 - Transmit Data Register
Control Register (Read/Write)
The Control Register (Figure 7) is used for general purpose control of the HDLC Protocol Controller. The bits
contained in this register and their functions are described below.
Rx FIFO
Status Bits
Status
D5
D4
0
Rx FIFO Empty
0
1
Less than or equal to 14 bytes
1
0
Rx FIFO Full
1
Greater than or equal to 15 bytes
Tx FIFO
Status Bits
Status
D3
D2
0
Tx FIFO Full
0
1
Greater than or equal to 5 bytes
1
0
Tx FIFO Empty
1
Less than or equal to 4 bytes
D7
D6
D5
D4
D3
D2
D1
D0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
D7
D6
D5
D4
D3
D2
D1
D0
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
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相关代理商/技术参数 |
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| MT8952BPR1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel |
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