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参数资料
| 型号： | MT8952BPR |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 6/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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MT8952B
Data Sheet
14
Zarlink Semiconductor Inc.
The C-Channel Register (Figure 13) continuously stores the data received during the channel-1 timeslot of the
incoming ST-BUS (CDSTi) during the Internal Timing Mode of the Protocol Controller.
Reset
When the MT8952B is reset by a low going pulse on the RST pin or by setting (logic high) the RST bit in the Timing
Control Register, the device is put into the following state:
a. All bits in the Timing Control Register are cleared (logic 0) by an external reset. An internal reset clears all
bits except the RST bit.
b. All bits in the Interrupt Enable Register are cleared (logic 0).
c. All bits in the Control Register are cleared (logic 0).
d. All bits in the Interrupt Register are cleared (logic 0).
e. All bits in the General Status Register are cleared (logic 0) except for the two least significant bits.
f. Receive and Transmit Registers are cleared and the FIFO Status Register reflects their state accordingly.
g. The WD output is reset low by an external reset but is not affected by an internal reset.
h. The Transmitter and the Receiver are disabled.
Transmit Operation
After a reset, which the external circuitry should provide upon power up, the transmit section is disabled. Before
enabling this section, the timing should be set up. On reset, the serial port is set to External Timing Mode. In case
this is not desired, the Timing Control Register should be written to with the appropriate data. Once in the correct
timing mode, the Transmit Enable (TxEN) bit in the Control Register can be set. Now that the transmitter is enabled
it will be in the Idle channel state. If any other channel state or the transparent data transfer facility is required, the
IFTF bits in the Control Register should be set accordingly.
Normal Packets
To start a packet, the data is written into the transmit FIFO starting with the address field. All the data must be
written to the FIFO in a bytewide manner. When the data is detected in the transmit FIFO, the protocol controller will
proceed in one of the following ways:
If the transmitter is in idle state, the present byte of eight ONEs being transmitted is completed and then followed
by a start flag and subsequently the data in the transmit FIFO is transmitted.
If the transmitter is in the interframe time fill state, the flag presently being transmitted is finished and then another
start flag is transmitted before transmitting the data from the transmit FIFO.
If the transmitter is in go ahead state, it continues to be in that state even after the data is loaded into the FIFO. Only
when the IFTF bits are set to choose something other than go ahead will the data be transmitted.
If the transmitter is in transparent data transfer state, the protocol functions are disabled and the data in the transmit
FIFO is transmitted on CDSTo.
To indicate that the particular byte is the last byte of the packet, the EOP bit in the Control Register must be set
before the last byte is written into the transmit FIFO. The EOP bit is cleared automatically when the data byte is
written to the FIFO. After the transmission of the last byte in the packet, the frame check sequence (16 bits) is sent
followed by a closing flag. If there is any more data in the transmit FIFO, another flag is transmitted followed by the
new data. In case of no data in the FIFO, the transmitter assumes the selected link channel state. During the
transmission of either the data or the frame check sequence, the Protocol Controller checks the transmitted
information on a bit by bit basis and inserts a ZERO after every sequence of five consecutive ONEs.
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相关代理商/技术参数 |
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| MT8952BPR1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel |
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