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参数资料
| 型号： | MT8952BPR |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封装： | PLASTIC, MS-018AB, LCC-28 |
| 文件页数： | 8/32页 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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MT8952B
Data Sheet
16
Zarlink Semiconductor Inc.
Receive Operation
After a reset on power up, the receive section is disabled. Timing set up considerations are similar to that of the
transmit section. Address detection is also disabled when a reset occurs. If address detection is required, the
Receiver Address Register is loaded with the desired address and the RxAD bit in the Control Register is set HIGH.
The receive section can then be enabled by RxEN bit in the Control Register.
Normal Packets
After initialization as explained above, the serial data starts to be clocked in and the receiver checks for the idle
channel and flags. If an idle channel is detected, the ‘Idle’ bit in the General Status Register is set HIGH. Once a
flag is detected, the receiver synchronizes itself in a bytewide manner to the incoming data stream. The receiver
keeps resynchronizing to the flags until an incoming packet appears. The incoming packet is examined on a bit-by-
bit basis, inserted zeros are deleted, the FCS is calculated and the data bytes are written into the receive FIFO.
However, the FCS and other control characters like the flag, abort etc., never appear in the FIFO. If the address
detection is enabled, the first byte following the flag is compared to the byte in the Receive Address Register and to
All-Call address. If a match is not found, the entire packet is ignored and nothing is written to the FIFO. If the
incoming address byte is valid, the packet is received in normal fashion. All the bytes written to the receive FIFO
are flagged with two status bits. The status bits are found in the FIFO status register and indicate whether the byte
to be read from the FIFO is the first byte of the packet, the middle of the packet, the last byte of the packet with
good FCS or the last byte of the packet with bad FCS. This status indication is valid for the byte to be read from the
receive FIFO.
The incoming data is always written to the FIFO in a bytewide manner. However, in the event of data sent not being
a multiple of eight bits, the software associated with the receiver should be able to pick the data bits from the MSB
positions of the last byte in the received data written to the FIFO. The Protocol Controller does not provide any
indication as to how many bits this might be.
Receive FIFO Empty
When the Receive FIFO is empty, this state is indicated by the Receive FIFO status bits in the FIFO Status
Register. As with the Tx FIFO status bits (see Transmit FIFO Full Section), these bits are not updated for two bit
periods after any access of the Receive FIFO. If the controlling microprocessor’s bus cycle is much shorter than a
bit period on the serial port, then the status bits may not be updated to indicate there is no information left in the Rx
FIFO before the microprocessor has returned to read the Rx FIFO again. The result is an underflow condition that is
only evident by redundant bytes in the received message.
To avoid a Rx FIFO underflow, reading information from the Rx FIFO should be approached in two ways. The first
approach is to be used when the MT8952B indicates (via interrupt) that the Rx FIFO is 15/19 FULL. The controlling
microprocessor should then immediately read 14 bytes from the Rx FIFO. This will avoid emptying the FIFO. The
second approach is to be used when an End of Packet interrupt is signalled by the MT8952B. The controlling
microprocessor should then empty the Rx FIFO until the Rx Byte Status bits in the FIFO Status Register indicate
that the byte about to be read is the last byte. These bits are “tag“ bits whose state was determined before the End
of Packet condition was indicated, therefore their state is valid.
Invalid Packets
If there are less than 24 data bits between the opening and closing flags, the packet is considered invalid and the
data never enters the receive FIFO. This is true even with data and the abort sequence, the total of which is less
than 24 bits. The data packets that are at least 24 bits but less than 32 bits long are also invalid, but not ignored.
They are clocked into the receive FIFO and tagged as having bad FCS.
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相关代理商/技术参数 |
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|---|---|
| MT8952BPR1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel |
| MT8952BS | 制造商:Microsemi Corporation 功能描述: |
| MT8952BS1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC PROTOCOL CONTROLLER - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC PROTOCOL CONTROLLER |
| MT8960 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Integrated PCM Filter Codec |
| MT8960AE | 制造商:ZARLINK 功能描述: |
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