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| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
Theory of Operation
The APD3212/NCP3218/NCP3218G combines multi ? mode
Pulse ? Width Modulated (PWM) control and Ramp ? Pulse
Modulated (RPM) control with multi ? phase logic outputs
for use in single ? , dual ? phase, or triple ? phase synchronous
buck CPU core supply power converters. The internal 7 ? bit
VID DAC conforms to the Intel IMVP ? 6.5 specifications.
Multi ? phase operation is important for producing the high
currents and low voltages demanded by today’s
microprocessors. Handling high currents in a single ? phase
converter would put too high of a thermal stress on system
components such as the inductors and MOSFETs.
The multimode control of the APD3212/NCP3218/
NCP3218G is a stable, high performance architecture that
includes
? Current and thermal balance between phases.
? High speed response at the lowest possible switching
frequency and minimal count of output decoupling
capacitors.
? Minimized thermal switching losses due to lower
frequency operation.
? High accuracy load line regulation.
? High current output by supporting 2 ? phase or 3 ? phase
operation.
? Reduced output ripple due to multi ? phase ripple
cancellation.
? High power conversion efficiency with heavy and light
loads.
? Increased immunity from noise introduced by PC board
layout constraints.
? Ease of use due to independent component selection.
? Flexibility in design by allowing optimization for either
low cost or high performance.
Number of Phases
The number of operational phases can be set by the user.
Tying the PH1 pin to the GND pin forces the chip into
single ? phase operation. Tying PH0 to GND and PH1 to
VCC forces the chip into 2 ? phase operation. Tying PH0 and
PH1 to VCC forces the chip in 3 ? phase operation. PH0 and
PH1 should be hard wired to VCC or GND. The
APD3212/NCP3218/NCP3218G switches between single
phase and multi ? phase operation with PSI and DPRSLP to
optimize power conversion efficiency. Table 1 summarizes
PH0 and PH1.
Table 1. PHASE NUMBER CONFIGURATION
monitors the PWM outputs. Because each phase is
monitored independently, operation approaching 100%
duty cycle is possible. In addition, more than one output can
be active at a time, permitting overlapping phases.
Operation Modes
The number of phases can be static (see the Number of
Phases section) or dynamically controlled by system signals
to optimize the power conversion efficiency with heavy and
light loads.
If APD3212/NCP3218/NCP3218G is configured for
mulit ? phase configuration, during a VID transient or with a
heavy load condition (indicated by DPRSLP being low and
PSI being high), the APD3212/NCP3218/NCP3218G runs
in multi ? phase, interleaved PWM mode to achieve minimal
V CORE output voltage ripple and the best transient
performance possible. If the load becomes light (indicated by
PSI being low or DPRSLP being high), APD3212/
NCP3218/NCP3218G switches to single ? phase mode to
maximize the power conversion efficiency.
In addition to changing the number of phases, the
APD3212/NCP3218/NCP3218G is also capable of
dynamically changing the control method. In dual ? phase
operation, the APD3212/NCP3218/NCP3218G runs in
PWM mode, where the switching frequency is controlled by
the master clock. In single ? phase operation (commanded by
the DPRSLP high state), the APD3212/NCP3218/
NCP3218G runs in RPM mode, where the switching
frequency is controlled by the ripple voltage appearing on
the COMP pin. In RPM mode, the DRVH1 pin is driven high
each time the COMP pin voltage rises to a voltage limit set
by the VID voltage and an external resistor connected
between the RPM pin and GND. In RPM mode, the
APD3212/NCP3218/NCP3218G turns off the low ? side
(synchronous rectifier) MOSFET when the inductor current
drops to 0. Turning off the low ? side MOSFETs at the zero
current crossing prevents reversed inductor current build up
and breaks synchronous operation of high ? and low ? side
switches. Due to the asynchronous operation, the switching
frequency becomes slower as the load current decreases,
resulting in good power conversion efficiency with very
light loads.
Table 2 summarizes how the APD3212/NCP3218/
NCP3218G dynamically changes the number of active
phases and transitions the operation mode based on system
signals and operating conditions.
GPU Mode
The APD3212/NCP3218/NCP3218G can be used to
PH0
PH1
Number of Phases Configured
power IMVP ? 6.5 GMCH. To configure the APD3212/
0 0 1
1 0 1 (GPU Mode)
0 1 2
1 1 3
In mulit ? phase configuration, the timing relationship
between the phases is determined by internal circuitry that
NCP3218/NCP3218G in GPU, connect PH1 to VCC and
connect PH0 to GND. In GPU mode, the
APD3212/NCP3218/NCP3218G operates in single phase
only. In GPU mode, the boot voltage is disabled. During
startup, the output voltage ramps up to the programmed VID
voltage. There is no other difference between GPU mode
and normal CPU mode.
http://onsemi.com
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