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参数资料
| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
ABSOLUTE MAXIMUM RATINGS
Parameter
V CC , PV CC1 , PV CC2
FBRTN, PGND1, PGND2
BST1, BST2, DRVH1, DRVH2
DC
t < 200 ns
BST1 to PV CC , BST2 to PV CC
DC
t < 200 ns
BST1 to SW1, BST2 to SW2
SW1, SW2
DC
t < 200 ns
DRVH1 to SW1, DRVH2 to SW2
DRVL1 to PGND1, DRVL2 to PGND2
DC
t < 200 ns
RAMP (in Shutdown)
All Other Inputs and Outputs
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance ( q JA ) 2 ? Layer Board
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
? 0.3 to +6.0
? 0.3 to +0.3
? 0.3 to +28
? 0.3 to +33
? 0.3 to +22
? 0.3 to +28
? 0.3 to +6.0
? 1.0 to +22
? 6.0 to +28
? 0.3 to +6.0
? 0.3 to +6.0
? 5.0 to +6.0
? 0.3 to +22
? 0.3 to +6.0
? 65 to +150
? 40 to +100
125
30.5
300
260
Unit
V
V
V
V
V
V
V
V
V
V
° C
° C
° C
° C/W
° C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
PIN ASSIGNMENT
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
EN
PWRGD
IMON
CLKEN
FBRTN
FB
COMP
TRDET
VARFREQ
VRTT
Description
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and
VRTT low, and pulls CLKEN high.
Power ? Good Output. Open ? drain output. A low logic state means that the output voltage is outside of the
VID DAC defined range.
Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to
FBRTN sets the current monitor gain.
Clock Enable Output. Open ? drain output. A low logic state enables the CPU internal PLL clock to lock to
the external clock.
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the
ground return for the VID DAC and the voltage error amplifier blocks.
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Transient Detect Output. This pin is pulled low when a load release transient is detected. During repetitive
load transients at high frequencies, this circuit optimally positions the maximum and minimum output
voltage into a specified loadline window.
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator
temperature at the remote sensing point exceeded a set alarm threshold level.
http://onsemi.com
3
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