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参数资料
| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 26/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
R CS1 + R CS k r CS1
r CS2 +
r CS1 +
1
* r * A r
r TH +
* r 1
The following procedure and expressions yield values for
R CS1 , R CS2 , and R TH (the thermistor value at 25 ° C) for a
given R CS value.
1. Select an NTC to be used based on its type and
value. Because the value needed is not yet
determined, start with a thermistor with a value
close to R CS and an NTC with an initial tolerance
of better than 5%.
2. Find the relative resistance value of the NTC at
two temperatures. The appropriate temperatures
will depend on the type of NTC, but 50 ° C and
90 ° C have been shown to work well for most types
of NTCs. The resistance values are called A (A is
R TH (50 ° C)/R TH (25 ° C)) and B (B is
R TH (90 ° C)/R TH (25 ° C)). Note that the relative
value of the NTC is always 1 at 25 ° C.
3. Find the relative value of R CS required for each of
the two temperatures. The relative value of R CS is
based on the percentage of change needed, which
is initially assumed to be 0.39%/ ° C in this
example.
The relative values are called r 1 (r 1 is 1/(1+ TC ×
(T 1 ? 25))) and r 2 (r 2 is 1/(1 + TC × (T 2 ? 25))),
where TC is 0.0039, T 1 is 50 ° C, and T 2 is 90 ° C.
4. Compute the relative values for r CS1 , r CS2 , and r TH
by using the following equations:
(A ? B) r 1 r 2 * A (1 ? B) r 2 ) B (1 ? A) r 1
A (1 * B) r 1 * B (1 * A) r 2 * (A * B)
(1 * A)
(eq. 8)
1 * r CS2 1 CS2
1
1
1 * r CS2 CS1
5. Calculate R TH = r TH × R CS , and then select a
thermistor of the closest value available. In
addition, compute a scaling factor k based on the
ratio of the actual thermistor value used relative to
the computed one:
6. Calculate values for R CS1 and R CS2 by using the
following equations:
(eq. 10)
R CS2 + R CS (1 * k) ) (k r CS2 )
For example, if a thermistor value of 100 k W is selected
in Step 1, an available 0603 ? size thermistor with a value
close to R CS is the Vishay NTHS0603N04 NTC thermistor,
which has resistance values of A = 0.3359 and B = 0.0771.
Using the equations in Step 4, r CS1 is 0.359, r CS2 is 0.729,
and r TH is 1.094. Solving for r TH yields 241 k W , so a
thermistor of 220 k W would be a reasonable selection,
making k equal to 0.913. Finally, R CS1 and R CS2 are found
to be 72.1 k W and 166 k W . Choosing the closest 1% resistor
for R CS2 yields 165 k W . To correct for this approximation,
73.3 k W is used for R CS1 .
C OUT Selection
The required output decoupling for processors and
platforms is typically recommended by Intel. For systems
containing both bulk and ceramic capacitors, however, the
following guidelines can be a helpful supplement.
Select the number of ceramics and determine the total
ceramic capacitance (C Z ). This is based on the number and
type of capacitors used. Keep in mind that the best location
to place ceramic capacitors is inside the socket; however, the
physical limit is twenty 0805 ? size pieces inside the socket.
Additional ceramic capacitors can be placed along the outer
edge of the socket. A combined ceramic capacitor value of
200 m F to 300 m F is recommended and is usually composed
of multiple 10 m F or 22 m F capacitors.
Ensure that the total amount of bulk capacitance (C X ) is
within its limits. The upper limit is dependent on the VID
OTF output voltage stepping (voltage step, V V , in time, t V ,
with error of V ERR ); the lower limit is based on meeting the
critical capacitance for load release at a given maximum load
step, D I O . The current version of the IMVP ? 6.5
specification allows a maximum V CORE overshoot
(V OSMAX ) of 10 mV more than the VID voltage for a
step ? off load current.
R O ) OSMAX
k +
R TH(ACTUAL)
R TH(CALCULATED)
(eq. 9)
C X(MIN) w
n
L D I O
V
D I O
V VID
* C Z
(eq. 11)
1 ) t v VID
C X(MAX) v
n
L
k 2
R O 2
V V
V VID
V
V V
n
k
L
R O
2
* 1 * C Z
where k + ? ln
http://onsemi.com
26
V ERR
V V
(eq. 12)
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