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参数资料
| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
ELECTRICAL CHARACTERISTICS
V CC = PV CC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,
V VID = V DAC = 1.2000 V, T A = ? 40 ° C to 100 ° C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positiv e sign.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
CURRENT MONITOR
Current Gain Accuracy
IMON Clamp Voltage
I MON /I LIM
V MAXMON
Measured from ILIM to IMON
I LIM = ? 20 m A
I LIM = ? 10 m A
I LIM = ? 5 m A
Relative to FBRTN, ILIMP = ? 30 m A
3.7
3.6
3.5
1.0
4.0
4.0
4.0
4.3
4.4
4.5
1.15
?
V
PULSE WIDTH MODULATOR
CLOCK OSCILLATOR
RT Voltage
PWM Clock Frequency Range
(Note 2)
PWM Clock Frequency
V RT
f CLK
f CLK
VARFREQ = high, R T = 125 k W ,
V VID = 1.5000 V
VARFREQ = low
See also V RT (V VID ) formula
Operation of interest
T A = +25 ° C, V VID = 1.2000 V
R T = 72 k W
R T = 120 k W
R T = 180 k W
1.125
0.9
0.3
1100
700
500
1.25
1.0
1257
800
550
1.375
1.1
3.0
1400
900
600
V
MHz
kHz
RAMP GENERATOR
RAMP Voltage
RAMP Current Range (Note 2)
V RAMP
I RAMP
EN = high, I RAMP = 60 m A
EN = low
EN = high
EN = low, RAMP = 19 V
0.9
1.0
? 1.0
1.0
V IN
1.1
100
+1.0
V
m A
PWM COMPARATOR
PWM Comparator Offset (Note 2)
V OSRPM
V RAMP ? V COMP
± 3.0
mV
RPM COMPARATOR
RPM Current
RPM Comparator Offset (Note 2)
I RPM
V OSRPM
V VID = 1.2 V, R T = 215 k W
See also I RPM (R T ) formula
V COMP ? (1 + V RPMTH )
? 9.0
± 3.0
m A
mV
EPWM CLOCK SYNC
Trigger Threshold (Note 2)
Relative to COMP sampled T CLK time
earlier
3 ? phase configuration
2 ? phase configuration
1 ? phase configuration
350
400
450
mV
TRDET
Trigger Threshold (Note 2)
Relative to COMP sampled T CLK time
earlier
3 ? phase configuration
2 ? phase configuration
1 ? phase configuration
? 450
? 500
? 600
mV
TRDET Low Voltage (Note 2)
TRDET Leakage Current
V LTRDET
I HTRDET
Logic low, I TRDETsink = 4 mA
Logic high, V TRDET = VCC
30
300
5.0
mV
m A
SWITCH AMPLIFIER
SW Common Mode Range
(Note 2)
V SW(X)CM
Operation of interest for current sensing
? 600
+200
mV
SWFB Input Resistance
R SW(X)
SW X = 0 V, SWFB = 0 V
20
35
50
k W
ZERO CURRENT SWITCHING COMPARATOR
SW ZCS Threshold
V DCM(SW1)
DCM mode, DPRSLP = 3.3 V
? 6.0
mV
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Guaranteed by design or bench characterization, not production tested.
Based on bench characterization data.
Timing is referenced to the 90% and 10% points, unless otherwise noted.
http://onsemi.com
7
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