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| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 17/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
R SWFB1
To increase the current in any given phase, users should
make RSWFB for that phase larger (that is, RSWFB = 100 W
for the hottest phase and do not change it during balance
optimization). Increasing RSWFB to 150 W makes a
substantial increase in phase current. Increase each RSWFB
value by small amounts to achieve thermal balance starting
with the coolest phase.
If adjusting current balance between phases is not needed,
RSWFB should be 100 W for all phases.
VDC
ADP3212 Phase 1
Inductor
SWFB1
33
VDC
PWRGD range is monitored. To prevent a false alarm, the
power ? good circuit is masked during various system
transitions, including a VID change and entrance into or exit
out of deeper sleep. The duration of the PWRGD mask is set
to approximately 130 m s by an internal timer. If the voltage
drop is greater than 200 mV during deeper sleep entry or
slow deeper sleep exit, the duration of PWRGD masking is
extended by the internal logic circuit.
Powerup Sequence and Soft ? Start
The power ? on ramp ? up time of the output voltage is set
internally. The APD3212/NCP3218/NCP3218G steps
sequentially through each VID code until it reaches the boot
voltage. The powerup sequence, including the soft ? start is
illustrated in Figure 20.
After EN is asserted high, the soft ? start sequence starts.
SWFB2
SWFB3
28
R SWFB3
24
R SWFB2
VDC
Phase 3
Inductor
Phase 2
Inductor
The core voltage ramps up linearly to the boot voltage. The
APD3212/NCP3218/NCP3218G regulates at the boot
voltage for approximately 90 m s. After the boot time is over,
CLKEN is asserted low. Before CLKEN is asserted low, the
VID pins are ignored. 9 ms after CLKEN is asserted low,
PWRGD is asserted high.
VCC = 5 V
EN
Figure 19. Current Balance Resistors
V BOOT
Voltage Control Mode
A high ? gain bandwidth error amplifier is used for the
voltage mode control loop. The non ? inverting input voltage
is set via the 7 ? bit VID DAC. The VID codes are listed in
Table 3. The non ? inverting input voltage is offset by the
droop voltage as a function of current, commonly known as
active voltage positioning. The output of the error amplifier
V CORE
PWRGD
t BOOT
CLKEN
t CPU_PWRGD
is the COMP pin, which sets the termination voltage of the
internal PWM ramps.
At the negative input, the FB pin is tied to the output sense
location using R B , a resistor for sensing and controlling the
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
Power ? Good Monitoring
The power ? good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open ? drain
output that can be pulled up through an external resistor to
a voltage rail; not necessarily the same VCC voltage rail that
is running the controller. A logic high level indicates that the
output voltage is within the voltage limits defined by a range
around the VID voltage setting. PWRGD goes low when the
output voltage is outside of this range.
Following the IMVP ? 6.5 specification, the PWRGD
range is defined to be 300 mV less than and 200 mV greater
than the actual VID DAC output voltage. For any DAC
voltage less than 300 mV, only the upper limit of the
Figure 20. Powerup Sequence of
APD3212/NCP3218/NCP3218G
Current Limit
The APD3212/NCP3218/NCP3218G compares the
differential output of a current sense amplifier to a
programmable current limit set point to provide the current
limiting function. The current limit threshold is set by the user
with a resistor connected from the ILIM pin to CSCOMP.
Changing VID On ? The ? Fly (OTF)
The APD3212/NCP3218/NCP3218G is designed to track
dynamically changing VID code. As a consequence, the
CPU VCC voltage can change without the need to reset the
controller or the CPU. This concept is commonly referred to
as VID OTF transient. A VID OTF can occur with either
light or heavy load conditions. The processor alerts the
controller that a VID change is occurring by changing the
VID inputs in LSB incremental steps from the start code to
the finish code. The change can be either upwards or
downwards steps.
http://onsemi.com
17
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