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| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 29/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
ripple and high frequency load transients. Since the IMON
pin is connected directly to the CPU, it is clamped to prevent
it from going above 1.15 V.
The IMON pin current is equal to the R LIM times a fixed
gain of 4. R MON can be found using the following equation:
Gain
? 20 dB/dec
R MON +
1.15 V
4 R O
R LIM
I FS
(eq. 21)
? 20 dB/dec
where:
f Z1 +
1
R A
2 p
C A
f Z2 +
1
R FB
2 p
C FB
R MON is the current monitor resistor. R MON is connected
from IMON pin to FBRTN.
R LIM is the current limit resistor.
R O is the output load line resistance.
I FS is the output current when the voltage on IMON is at full
scale.
Feedback Loop Compensation Design
Optimized compensation of the APD3212/NCP3218/
NCP3218G allows the best possible response of the
regulator ’s output to a load change. The basis for
determining the optimum compensation is to make the
0 dB
f Z1 f P0 f P1 f Z2 Frequency
Figure 32. Poles and Zeros of Voltage Error Amplifier
The following equations give the locations of the poles
and zeros shown in Figure 32:
(eq. 22)
(eq. 23)
regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and that is equal to the droop
resistance (R O ). With the resistive output impedance, the
output voltage droops in proportion with the load current at
f P0 +
f P1 +
2 p
2 p
1
(C A ) C B )
C A ) C B
R A C B
R FB
C A
(eq. 24)
(eq. 25)
R E + n
R O ) A D
R DS )
R L V RT
V VID
2
L
(1 * (n
D))
V RT
any load current slew rate, ensuring the optimal position and
allowing the minimization of the output decoupling.
With the multimode feedback structure of the
APD3212/NCP3218/NCP3218G, it is necessary to set the
feedback compensation so that the converter ’s output
impedance works in parallel with the output decoupling. In
addition, it is necessary to compensate for the several poles
and zeros created by the output inductor and decoupling
capacitors (output filter).
A Type III compensator on the voltage feedback is
The expressions that follow compute the time constants
for the poles and zeros in the system and are intended to yield
an optimal starting point for the design; some adjustments
may be necessary to account for PCB and component
parasitic effects (see the Tuning Procedure for 12 section):
)
(eq. 26)
n C X R O V VID
REFERENCE
T A + C X
(R O * R ) )
A D R DS
2 f SW
T C +
adequate for proper compensation of the output filter.
Figure 31 shows the Type III amplifier used in the
APD3212/NCP3218/NCP3218G. Figure 32 shows the
locations of the two poles and two zeros created by this
amplifier.
VOLTAGE ERROR
AMPLIFIER VOLTAGE
T B + (R X ) R * R O ) C X
V RT L *
V VID R E
L X
R O
R O * R
R X
(eq. 27)
(eq. 28)
(eq. 29)
COMP
FB
ADP3212
T D +
C X
C X C Z R O 2
(R O * R ) ) C Z
R O
(eq. 30)
C FB
C A
OUTPUT
R A VOLTAGE
C B R FB
Figure 31. Voltage Error Amplifier
where:
R ′ is the PCB resistance from the bulk capacitors to the
ceramics and is approximately 0.4 m W (assuming an 8 ? layer
motherboard).
R DS is the total low ? side MOSFET for on resistance per
phase.
A D is 5.
V RT is 1.25 V.
L X is 150 pH for the six Panasonic SP capacitors.
http://onsemi.com
29
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