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| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 18/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
When a VID input changes, the APD3212/NCP3218/
NCP3218G detects the change but ignores new code for a
minimum of 400 ns. This delay is required to prevent the
device from reacting to digital signal skew while the 7 ? bit
VID input code is in transition. Additionally, the VID
change triggers a PWRGD masking timer to prevent a
PWRGD failure. Each VID change resets and retriggers the
internal PWRGD masking timer.
As listed in Table 3, during a VID transient, the
APD3212/NCP3218/NCP3218G forces PWM mode
regardless of the state of the system input signals. For
example, this means that if the chip is configured as a
dual ? phase controller but is running in single ? phase mode
due to a light load condition, a current overload event causes
the chip to switch to dual ? phase mode to share the excessive
load until the delayed current limit latchoff cycle terminates.
In user ? set single ? phase mode, the APD3212/NCP3218/
NCP3218G usually runs in RPM mode. When a VID
transition occurs, however, the APD3212/NCP3218/
NCP3218G switches to dual ? phase PWM mode.
Light Load RPM DCM Operation
In single ? phase normal mode, DPRSLP is pulled low and
the APD3208 operates in Continuous Conduction Mode
(CCM) over the entire load range. The upper and lower
MOSFETs run synchronously and in complementary phase.
In DCM with a light load, the APD3212/NCP3218/
NCP3218G monitors the switch node voltage to determine
when to turn off the low ? side FET. Figure 27 shows a typical
waveform in DCM with a 1 A load current. Between t 1 and
t 2 , the inductor current ramps down. The current flows
through the source drain of the low ? side FET and creates a
voltage drop across the FET with a slightly negative switch
node. As the inductor current ramps down to 0 A, the switch
voltage approaches 0 V, as seen just before t 2 . When the
switch voltage is approximately ? 6 mV, the low ? side FET is
turned off.
Figure 26 shows a small, dampened ringing at t 2 . This is
caused by the LC created from capacitance on the switch
node, including the C DS of the FETs and the output inductor.
This ringing is normal.
The APD3212/NCP3218/NCP3218G automatically goes
into DCM with a light load. Figure 27 shows the typical
DCM waveform of the APD3212/NCP3218/NCP3218G.
As the load increases, the APD3212/NCP3218/NCP3218G
enters into CCM. In DCM, frequency decreases with load
current. Figure 28 shows switching frequency vs. load
current for a typical design. In DCM, switching frequency
is a function of the inductor, load current, input voltage, and
output voltage.
Q1
See Figure 21 for the typical waveforms of the
APD3212/NCP3218/NCP3218G running in CCM with a 7
INPUT
VOLTAGE
DRVH
SWITCH
NODE
OUTPUT
VOLTAGE
A load current.
Q2
DRVL
L
C
LOAD
4
OUTPUT VOLTAGE
2
20 mV/DIV
INDUCTOR CURRENT
5 A/DIV
SWITCH NODE 5 V/DIV
Figure 22. Buck Topology
ON
L
3
LOW ? SIDE GATE DRIVE 5 V/DIV
OFF
C
LOAD
1
400 ns/DIV
Figure 23. Buck Topology Inductor Current
During t 0 and t 1
Figure 21. Single ? Phase Waveforms in CCM
OFF
L
If DPRSLP is pulled high, the APD3212/NCP3218/
NCP3218G operates in RPM mode. If the load condition is
ON
C
LOAD
light, the chip enters Discontinuous Conduction Mode
(DCM). Figure 22 shows a typical single ? phase buck with
one upper FET, one lower FET, an output inductor, an output
capacitor, and a load resistor. Figure 23 shows the path of the
Figure 24. Buck Topology Inductor Current
During t 1 and t 2
inductor current with the upper FET on and the lower FET
off. In Figure 24, the high ? side FET is off and the low ? side
OFF
L
FET is on. In CCM, if one FET is on, its complementary FET
must be off; however, in DCM, both high ? and low ? side
OFF
C
LOAD
FETs are off and no current flows into the inductor (see
Figure 25). Figure 26 shows the inductor current and switch
node voltage in DCM.
Figure 25. Buck Topology Inductor Current During
t 2 and t 3
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