参数资料
型号: NCP3218MNR2G
厂商: ON Semiconductor
文件页数: 32/35页
文件大小: 0K
描述: IC CTLR BUCK 7BIT 3PHASE 48QFN
标准包装: 2,500
应用: 控制器,Intel IMVP-6.5?
输入电压: 3.3 V ~ 22 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-QFN(6x6)
包装: 带卷 (TR)
其它名称: NCP3218MNR2G-ND
NCP3218MNR2GOSTR
ADP3212, NCP3218, NCP3218G
dynamic loads have an excessive overshoot at
powerup if a minimum current is incorrectly set
(this is an issue if a VTT tool is in use).
Set the Initial Transient
1. With the dynamic load set at its maximum step
V TRANREL
V DROOP
size, expand the scope time scale to 2 m s/div to
5 m s/div. This results in a waveform that may have
two overshoots and one minor undershoot before
achieving the final desired value after V DROOP
(see Figure 36).
Figure 37. Transient Setting Waveform, Load Release
V DROOP
Layout and Component Placement
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
V TRAN1
V TRAN2
1. For best results, use a PCB of four or more layers.
This should provide the needed versatility for
control circuitry interconnections with optimal
placement; power planes for ground, input, and
Figure 36. Transient Setting Waveform, Load Step
2. If both overshoots are larger than desired, try the
following adjustments in the order shown.
a. Increase the resistance of the ramp resistor
(R RAMP ) by 25%.
b. For V TRAN1 , increase C B or increase the switching
frequency.
c. For V TRAN2 , increase R A by 25% and decrease C A
by 25%.
If these adjustments do not change the response, it is
because the system is limited by the output
decoupling. Check the output response and the
switching nodes each time a change is made to
ensure that the output decoupling is stable.
3. For load release (see Figure 37), if V TRANREL is
larger than the value specified by IMVP ? 6.5, a
greater percentage of output capacitance is needed.
Either increase the capacitance directly or decrease
the inductor values. (If inductors are changed,
however, it will be necessary to redesign the
circuit using the information from the spreadsheet
and to repeat all tuning guide procedures).
output; and wide interconnection traces in the rest
of the power delivery current paths. Keep in mind
that each square unit of 1 oz copper trace has a
resistance of ~0.53 m W at room temperature.
2. When high currents must be routed between PCB
layers, vias should be used liberally to create
several parallel current paths so that the resistance
and inductance introduced by these current paths is
minimized and the via current rating is not
exceeded.
3. If critical signal lines (including the output voltage
sense lines of the APD3212/NCP3218/
NCP3218G) must cross through power circuitry, it
is best if a signal ground plane can be interposed
between those signal lines and the traces of the
power circuitry. This serves as a shield to
minimize noise injection into the signals at the
expense of increasing signal ground noise.
4. An analog ground plane should be used around
and under the APD3212/NCP3218/NCP3218G for
referencing the components associated with the
controller. This plane should be tied to the nearest
ground of the output decoupling capacitor, but
should not be tied to any other power circuitry to
prevent power currents from flowing into the
plane.
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