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参数资料
| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 33/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
5. The components around the APD3212/NCP3218/
NCP3218G should be located close to the
controller with short traces. The most important
traces to keep short and away from other traces are
those to the FB and CSSUM pins. Refer to
Figure 30 for more details on the layout for the
CSSUM node.
6. The output capacitors should be connected as close
as possible to the load (or connector) that receives
the power (for example, a microprocessor core). If
the load is distributed, the capacitors should also
be distributed and generally placed in greater
proportion where the load is more dynamic.
7. Avoid crossing signal lines over the switching
power path loop, as described in the Power
Circuitry section.
8. Connect a 1 m F decoupling ceramic capacitor from
VCC to GND. Place this capacitor as close as
possible to the controller. Connect a 4.7 m F
decoupling ceramic capacitor from PVCC to
PGND. Place capacitor as close as possible to the
controller.
Power Circuitry
1. The switching power path on the PCB should be
routed to encompass the shortest possible length to
minimize radiated switching noise energy (that is,
EMI) and conduction losses in the board. Failure
to take proper precautions often results in EMI
problems for the entire PC system as well as
noise ? related operational problems in the
power ? converter control circuitry. The switching
power path is the loop formed by the current path
through the input capacitors and the power
MOSFETs, including all interconnecting PCB
traces and planes. The use of short, wide
interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance
in the switching loop, which can cause high energy
ringing, and it accommodates the high current
demand with minimal voltage loss.
2. When a power ? dissipating component (for
example, a power MOSFET) is soldered to a PCB,
ORDERING INFORMATION
the liberal use of vias, both directly on the
mounting pad and immediately surrounding it, is
recommended. Two important reasons for this are
improved current rating through the vias and
improved thermal performance from vias extended
to the opposite side of the PCB, where a plane can
more readily transfer heat to the surrounding air.
To achieve optimal thermal dissipation, mirror the
pad configurations used to heat sink the MOSFETs
on the opposite side of the PCB. In addition,
improvements in thermal performance can be
obtained using the largest possible pad area.
3. The output power path should also be routed to
encompass a short distance. The output power path
is formed by the current path through the inductor,
the output capacitors, and the load.
4. For best EMI containment, a solid power ground
plane should be used as one of the inner layers and
extended under all power components.
Signal Circuitry
1. The output voltage is sensed and regulated
between the FB and FBRTN pins, and the traces of
these pins should be connected to the signal
ground of the load. To avoid differential mode
noise pickup in the sensed signal, the loop area
should be as small as possible. Therefore, the FB
and FBRTN traces should be routed adjacent to
each other, atop the power ground plane, and back
to the controller.
2. The feedback traces from the switch nodes should
be connected as close as possible to the inductor.
The CSREF signal should be Kelvin connected to
the center point of the copper bar, which is the
V CORE common node for the inductors of all the
phases.
3. On the back of the APD3212/NCP3218/
NCP3218G package, there is a metal pad that can
be used to heat sink the device. Therefore, running
vias under the APD3212/NCP3218/NCP3218G is
not recommended because the metal pad may
cause shorting between vias.
Device Number*
ADP3212MNR2G
NCP3218MNR2G
NCP3218MNTWG
NCP3218GMNR2G
Temperature Range
? 40 ° C to 100 ° C
? 40 ° C to 100 ° C
? 40 ° C to 100 ° C
? 40 ° C to 100 ° C
Package
48 ? Lead Frame Chip Scale Pkg [QFN_VQ]
7x7 mm, 0.5 mm pitch
48 ? Lead Frame Chip Scale Pkg [QFN_VQ]
6x6 mm, 0.4 mm pitch
48 ? Lead Frame Chip Scale Pkg [QFN_VQ]
6x6 mm, 0.4 mm pitch
48 ? Lead Frame Chip Scale Pkg [QFN_VQ]
6x6 mm, 0.4 mm pitch
Package Option
CP ? 48 ? 1
CP ? 48 ? 1
CP ? 48 ? 1
CP ? 48 ? 1
Shipping ?
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
?For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*The “G’’ suffix indicates Pb ? Free package.
http://onsemi.com
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