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参数资料
| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 27/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
I O
) 1
n SF
n SF
P SF + (1 ? D) R DS(SF)
To meet the conditions of these expressions and the
transient response, the ESR of the bulk capacitor bank (R X )
should be less than two times the droop resistance, R O . If the
C X(MIN) is greater than C X(MAX) , the system does not meet
the VID OTF and/or the deeper sleep exit specifications and
may require less inductance or more phases. In addition, the
switching frequency may have to be increased to maintain
the output ripple.
For example, if 30 pieces of 10 m F, 0805 ? size MLC
capacitors (C Z = 300 m F) are used, the fastest VID voltage
change is when the device exits deeper sleep, during which
the V CORE change is 220 mV in 22 m s with a setting error of
10 mV. If k = 3.1, solving for the bulk capacitance yields
C X(MIN) w
the APD3212/NCP3218/NCP3218G, currents are balanced
between phases; the current in each low ? side MOSFET is
the output current divided by the total number of MOSFETs
(n SF ). With conduction losses being dominant, the following
expression shows the total power that is dissipated in each
synchronous MOSFET in terms of the ripple current per
phase (I R ) and the average total output current (I O ):
2 2
n I R
12
(eq. 14)
where:
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
* 300 m F + 1.0 mF
2.1 m W )
1.4375 V
I R +
f SW
2
C X(MAX) v
330 nH 27.9 A
10 mV
27.9 A
330 nH 220 mV
2 3.1 2 (2.1 m W ) 2 1.4375 V
I R is the inductor peak ? to ? peak ripple current and is
approximately
(1 * D) V OUT
L
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the
1 )
22 m s 1.4375V 2 3.1 2.1m W
220 mV
490 nH
L X v C Z R O 2 Q 2
2
? 1 ? 300 m F
+ 21 mF
Using six 330 m F Panasonic SP capacitors with a typical
ESR of 7 m W each yields C X = 1.98 mF and R X = 1.2 m W .
Ensure that the ESL of the bulk capacitors (L X ) is low
enough to limit the high frequency ringing during a load
change. This is tested using:
(eq. 13)
L X v 300 m F (2.1 m W ) 2 2 + 2 nH
where:
Q is limited to the square root of 2 to ensure a critically
damped system.
L X is about 150 pH for the six SP capacitors, which is low
enough to avoid ringing during a load change. If the L X of
the chosen bulk capacitor bank is too large, the number of
ceramic capacitors may need to be increased to prevent
excessive ringing.
For this multimode control technique, an all ceramic
capacitor design can be used if the conditions of
Equations 11, 12, and 13 are satisfied.
Power MOSFETs
required R DS(ON) for the MOSFET. For 8 ? lead SOIC or
8 ? lead SOIC compatible MOSFETs, the junction ? to ?
ambient (PCB) thermal impedance is 50 ° C/W. In the worst
case, the PCB temperature is 70 ° C to 80 ° C during heavy
load operation of the notebook, and a safe limit for P SF is
about 0.8 W to 1.0 W at 120 ° C junction temperature.
Therefore, for this example (40 A maximum), the R DS(SF) per
MOSFET is less than 8.5 m W for two pieces of low ? side
MOSFETs. This R DS(SF) is also at a junction temperature of
about 120 ° C; therefore, the R DS(SF) per MOSFET should be
less than 6 m W at room temperature, or 8.5 m W at high
temperature.
Another important factor for the synchronous MOSFET
is the input capacitance and feedback capacitance. The ratio
of the feedback to input must be small (less than 10% is
recommended) to prevent accidentally turning on the
synchronous MOSFETs when the switch node goes high.
The high ? side (main) MOSFET must be able to handle
two main power dissipation components: conduction losses
and switching losses. Switching loss is related to the time for
the main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed
on the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression
provides an approximate value for the switching loss per
main MOSFET:
For typical 20 A per phase applications, the N ? channel
power MOSFETs are selected for two high ? side switches
and two or three low ? side switches per phase. The main
P S(MF) + 2
f SW
V DC
n MF
I O
R G
n MF
n
C ISS
(eq. 15)
selection parameters for the power MOSFETs are V GS(TH) ,
Q G , C ISS , C RSS , and R DS(ON) . Because the voltage of the
gate driver is 5.0 V, logic ? level threshold MOSFETs must be
used.
The maximum output current, I O , determines the R DS(ON)
requirement for the low ? side (synchronous) MOSFETs. In
where:
n MF is the total number of main MOSFETs.
R G is the total gate resistance.
C ISS is the input capacitance of the main MOSFET.
http://onsemi.com
27
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