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| 型号： | NCP3218MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/35页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 7BIT 3PHASE 48QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel IMVP-6.5? |
| 输入电压： | 3.3 V ~ 22 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
| 其它名称： | NCP3218MNR2G-ND NCP3218MNR2GOSTR |
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ADP3212, NCP3218, NCP3218G
exceeds the RPM pin voltage threshold level determined by
the VID voltage and the external resistor RPM resistor, an
internal ramp signal is started and DRVH1 is driven high.
The slew rate of the internal ramp is programmed by the
current entering the RAMP pin. One ? third of the RAMP
current charges an internal ramp capacitor (5 pF typical) and
creates a ramp. When the internal ramp signal intercepts the
COMP voltage, the DRVH1 pin is reset low.
Differential Sensing of Output Voltage
The APD3212/NCP3218/NCP3218G combines differential
sensing with a high accuracy VID DAC, referenced by a
precision band gap source and a low offset error amplifier,
to meet the rigorous accuracy requirement of the Intel
IMVP ? 6.5 specification. In steady ? state mode, the
combination of the VID DAC and error amplifier maintain
the output voltage for a worst ? case scenario within ± 8 mV
of the full operating output voltage and temperature range.
The CPU core output voltage is sensed between the FB
and FBRTN pins. FB should be connected through a resistor
to the positive regulation point; the VCC remote sensing pin
of the microprocessor. FBRTN should be connected directly
to the negative remote sensing point; the V SS sensing point
of the CPU. The internal VID DAC and precision voltage
reference are referenced to FBRTN and have a maximum
current of 200 m A for guaranteed accurate remote sensing.
Output Current Sensing
The APD3212/NCP3218/NCP3218G includes a
dedicated Current Sense Amplifier (CSA) to monitor the
total output current of the converter for proper voltage
positioning vs. load current and for over current detection.
Sensing the current delivered to the load is an inherently
more accurate method than detecting peak current or
sampling the current across a sense element, such as the
low ? side MOSFET. The current sense amplifier can be
configured several ways, depending on system optimization
objectives, and the current information can be obtained by:
? Output inductor ESR sensing without the use of a
thermistor for the lowest cost.
? Output inductor ESR sensing with the use of a
thermistor that tracks inductor temperature to improve
accuracy.
? Discrete resistor sensing for the highest accuracy.
At the positive input of the CSA, the CSREF pin is
connected to the output voltage. At the negative input (that
is, the CSSUM pin of the CSA), signals from the sensing
element (in the case of inductor DCR sensing, signals from
the switch node side of the output inductors) are summed
together by series summing resistors. The feedback resistor
between the CSCOMP and CSSUM pins sets the gain of the
current sense amplifier, and a filter capacitor is placed in
parallel with this resistor. The current information is then
given as the voltage difference between the CSCOMP and
CSREF pins. This signal is used internally as a differential
input for the current limit comparator.
An additional resistor divider connected between the
CSCOMP and CSREF pins with the midpoint connected to
the LLINE pin can be used to set the load line required by the
microprocessor specification. The current information to set
the load line is then given as the voltage difference between
the LLINE and CSREF pins. This configuration allows the
load line slope to be set independent from the current limit
threshold. If the current limit threshold and load line do not
have to be set independently, the resistor divider between the
CSCOMP and CSREF pins can be omitted and the
CSCOMP pin can be connected directly to LLINE. To
disable voltage positioning entirely (that is, to set no load
line), LLINE should be tied to CSREF.
To provide the best accuracy for current sensing, the CSA
has a low offset input voltage and the sensing gain is set by
an external resistor ratio.
Active Impedance Control Mode
To control the dynamic output voltage droop as a function
of the output current, the signal that is proportional to the
total output current, converted from the voltage difference
between LLINE and CSREF, can be scaled to be equal to the
required droop voltage. This droop voltage is calculated by
multiplying the droop impedance of the regulator by the
output current. This value is used as the control voltage of
the PWM regulator. The droop voltage is subtracted from the
DAC reference output voltage, and the resulting voltage is
used as the voltage positioning set point. The arrangement
results in an enhanced feed forward response.
Current Control Mode and Thermal Balance
The APD3212/NCP3218/NCP3218G has individual
inputs for monitoring the current of each phase. The phase
current information is combined with an internal ramp to
create a current ? balancing feedback system that is
optimized for initial current accuracy and dynamic thermal
balance. The current balance information is independent
from the total inductor current information used for voltage
positioning described in the Active Impedance Control
Mode section.
The magnitude of the internal ramp can be set so that the
transient response of the system is optimal. The
APD3212/NCP3218/NCP3218G monitors the supply
voltage to achieve feed forward control whenever the supply
voltage changes. A resistor connected from the power input
voltage rail to the RAMP pin determines the slope of the
internal PWM ramp. More detail about programming the
ramp is provided in the Application Information section.
External resistors are placed in series with the SWFB1,
SWFB2, and SWFB3 pins to create an intentional current
imbalance. Such a condition can exist when one phase has
better cooling and supports higher currents the other phases.
Resistors RSWSB1, RSWFB2, and RSWFB3 (see
Figure 25) can be used to adjust thermal balance. It is
recommended to add these resistors during the initial design
to make sure placeholders are provided in the layout.
http://onsemi.com
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