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参数资料
| 型号： | PADS1298CZXGT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封装： | 8 X 8 MM, LEAD FREE, PLASTIC, NFBGA-64 |
| 文件页数： | 21/73页 |
| 文件大小： | 957K |
| 代理商： | PADS1298CZXGT |
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PRODUCTPREVIEW
STAR
co
TOp
de
STARTPin
DN
I
4/f
CLK
DRDY
or
t
DR
t
SETTLE
SBAS459C – JANUARY 2010 – REVISED MARCH 2010
www.ti.com
Reset (RESET)
There are two methods to reset the ADS1294/6/8: pull the RESET pin low, or send the RESET opcode
command. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width
timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth
SCLK falling edge of the opcode command. On reset it takes 18 CLK cycles to complete initialization of the
configuration registers to the default states and start the conversion cycle. Note that an internal RESET is
automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to a new value with a
WREG command.
START
The START pin or the START command can be used to control conversions. START must be high or the START
command must be sent to be able to read conversion data from the device. When START is low and the START
command is not sent, the device does not issue a DRDY signal.
When using the START opcode to control conversion, hold the START pin low. The ADS1294/6/8 features two
modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT
(bit 3 of the CONFIG4 register). In multiple device configurations the START pin is used to synchronize devices
(see the Multiple Device Configuration subsection of the SPI Interface section for more details).
Settling Time
The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when START signal is
pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates that
data are ready. Figure 24 shows the timing diagram and Table 9 shows the settling time for different data rates.
The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Table 8 shows the settling time as a function of tCLK. Note that when START is held high and there is a
step change in the input signal, it takes 3 × tDR for the filter to settle to the new value. This time must be
considered when trying to measure narrow pace pulses for pacer detection.
Figure 24. Settling Time
Table 9. Settling Time for Different Data Rates
DR[2:0]
HIGH-RESOLUTION MODE
LOW-POWER MODE
UNIT
000
296
584
tCLK
001
584
1160
tCLK
010
1160
2312
tCLK
011
2312
4616
tCLK
100
4616
9224
tCLK
101
9224
18440
tCLK
110
18440
36872
tCLK
28
Copyright 2010, Texas Instruments Incorporated
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