参数资料
型号: PADS1298CZXGT
厂商: TEXAS INSTRUMENTS INC
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PBGA64
封装: 8 X 8 MM, LEAD FREE, PLASTIC, NFBGA-64
文件页数: 29/73页
文件大小: 957K
代理商: PADS1298CZXGT
PRODUCTPREVIEW
START
DRDY
CS
SCLK
DIN
t
UPDATE
DOUT
Hi-Z
RDATACOpcode
StatusRegister+8-ChannelData(216Bits)
NextData
www.ti.com
SBAS459C – JANUARY 2010 – REVISED MARCH 2010
STOP: Stop Conversions
This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP
command is sent, the conversion in progress completes and further conversions are stopped. If conversions are
already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it
can be issued any time.
RDATAC: Read Data Continuous
This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read
data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The
read data continuous mode is the default mode of the device and the device defaults in this mode on power-up.
RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a
SDATAC command must be issued before any other commands can be sent to the device. There is no
restriction on the SCLK rate for this command. However, the following data retrieval SCLKs or the SDATAC
opcode command should wait at least 4 CLK cycles. The timing for RDATAC is shown in Figure 30. As Figure 30
shows, there is a keep out zone of 4 CLK cycles around the DRDY pulse where this command cannot be issued
in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from
the device after RDATAC command is issued, make sure either the START pin is high or the START command
is issued. Figure 30 shows the recommended way to use the RDATAC command.
(1)
tUPDATE = 4/fCLK. Do not read data during this time.
Figure 30. RDATAC Usage
SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this
command, but the following command must wait for 4 CLK cycles.
Copyright 2010, Texas Instruments Incorporated
35
Product Folder Link(s): ADS1294 ADS1296 ADS1298
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