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| 型号： | PADS1298CZXGT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封装： | 8 X 8 MM, LEAD FREE, PLASTIC, NFBGA-64 |
| 文件页数： | 24/73页 |
| 文件大小： | 957K |
| 代理商： | PADS1298CZXGT |
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PRODUCTPREVIEW
START
DRDY
4f
/
CLK
4f
/
CLK
DataUpdating
t
SETTLE
SBAS459C – JANUARY 2010 – REVISED MARCH 2010
www.ti.com
Single-Shot Mode
The single-shot mode is set by setting SINGLE_SHOT bit in CONFIG4 register to '1'. In single-shot mode, the
ADS1294/6/8 perform a single conversion when the START pin is taken high or when the START opcode
command is sent. As seen in Figure 26, when a conversion is complete, DRDY goes low and further conversions
are stopped. Regardless of whether the conversion data are read or not, DRDY remains low. To begin a new
conversion, take the START pin low and then back high, or transmit the START opcode again. Note that when
switching from continuous mode to pulse mode, make sure the START signal is pulsed or issue a STOP
command followed by a START command.
Figure 27. DRDY with No Data Retrieval in Single-Shot Mode
MULTIPLE DEVICE CONFIGURATION
The ADS1294/6/8 are designed to provide configuration flexibility when multiple devices are used in a system.
The SPI interface typically needs four signals DIN, DOUT, SCLK, and CS. With one additional chip select signal
per device, multiple devices can be connected together. The number of signals needed to interface n devices is
3 + n.
The right-leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices
subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration,
one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL
pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit. This master
device clock is used as the external clock source for the other devices.
30
Copyright 2010, Texas Instruments Incorporated
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