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| 型号： | PADS1298CZXGT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封装： | 8 X 8 MM, LEAD FREE, PLASTIC, NFBGA-64 |
| 文件页数： | 32/73页 |
| 文件大小： | 957K |
| 代理商： | PADS1298CZXGT |
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PRODUCTPREVIEW
SBAS459C – JANUARY 2010 – REVISED MARCH 2010
www.ti.com
REGISTER MAP
Table 12 describes the various ADS1294/6/8 registers.
Table 12. Register Assignments
RESET
VALUE
ADDRESS
REGISTER
(Hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Device Settings (Read-Only Registers)
00h
xx
REV_ID3
REV_ID2
REV_ID1
N/A
DEV_ID2
DEV_ID1
NU_CH2
NU_CH1
Global Settings Across Channels
01h
06
HR
DAISY_EN
CLK_EN
0
DR2
DR1
DR0
02h
40
0
1
(1)
0
INT_TEST
0
TEST_AMP
TEST_FREQ1
TEST_FREQ0
RLD_LOFF_
03h
40
PD_REFBUF
1
VREF_4V
RLD_MEAS
RLDREF_INT
PD_RLD
RLD_STAT
SENS
VLEAD_OFF_
04h
00
COMP_TH2
COMP_TH1
COMP_TH0
ILEAD_OFF1
ILEAD_OFF0
FLEAD_OFF1
FLEAD_OFF0
EN
Channel-Specific Settings
05h
00
PD1
GAIN12
GAIN11
GAIN10
0
MUXn2
MUXn1
MUXn0
06h
00
PD2
GAIN22
GAIN21
GAIN20
0
MUX22
MUX21
MUX20
07h
00
PD3
GAIN32
GAIN31
GAIN30
0
MUX32
MUX31
MUX30
08h
00
PD4
GAIN42
GAIN41
GAIN40
0
MUX42
MUX41
MUX40
09h
CH5SET
(2)
00
PD5
GAIN52
GAIN51
GAIN50
0
MUX52
MUX51
MUX50
0Ah
CH6SET
(2)
00
PD6
GAIN62
GAIN61
GAIN60
0
MUX62
MUX61
MUX60
0Bh
CH7SET
(2)
00
PD7
GAIN72
GAIN71
GAIN70
0
MUX72
MUX71
MUX70
0Ch
CH8SET
(2)
00
PD8
GAIN82
GAIN81
GAIN80
0
MUX82
MUX81
MUX80
0Dh
(3)
00
RLD8P
(2)
RLD7P
(2)
RLD6P
(2)
RLD5P
(2)
RLD4P
RLD3P
RLD2P
RLD1P
0Eh
(3)
00
RLD8N
(2)
RLD7N
(2)
RLD6N
(2)
RLD5N
(2)
RLD4N
RLD3N
RLD2N
RLD1N
0Fh
(3)
00
LOFF8P
LOFF7P
LOFF6P
LOFF5P
LOFF4P
LOFF3P
LOFF2P
LOFF1P
10h
(3)
00
LOFF8N
LOFF7N
LOFF6N
LOFF5N
LOFF4N
LOFF3N
LOFF2N
LOFF1N
11h
00
LOFF_FLIP8
LOFF_FLIP7
LOFF_FLIP6
LOFF_FLIP5
LOFF_FLIP4
LOFF_FLIP3
LOFF_FLIP2
LOFF_FLIP1
Lead-Off Status Registers (Read-Only Registers)
12h
00
IN8P_OFF
IN7P_OFF
IN6P_OFF
IN5P_OFF
IN4P_OFF
IN3P_OFF
IN2P_OFF
IN1P_OFF
13h
00
IN8N_OFF
IN7N_OFF
IN6N_OFF
IN5N_OFF
IN4N_OFF
IN3N_OFF
IN2N_OFF
IN1N_OFF
GPIO and OTHER Registers
14h
0F
GPIOD4
GPIOD3
GPIOD2
GPIOD1
GPIOC4
GPIOC3
GPIOC2
GPIOC1
15h
00
0
PACEE1
PACEE0
PACEO1
PACEO0
PD_PACE
RESP_
RESP_MOD_
16h
00
RESP_PH2
RESP_PH1
RESP_PH0
RESP_CTRL1
RESP_CTRL0
DEMOD_EN1
EN1
VREFP
SINGLE_
WCT_TO_
PD_LOFF_
17h
00
RESP_FREQ2
RESP_FREQ1
RESP_FREQ0
0
SHOT
RLD
COMP
18h
00
aVF_CH6
aVL_CH5
aVR_CH7
avR_CH4
PD_WCTA
WCTA2
WCTA1
WCTA0
19h
00
PD_WCTC
PD_WCTB
WCTB2
WCTB1
WCTB0
WCTC2
WCTC1
WCTC0
(1)
This register bit must be written to '0' at power-up.
(2)
CH5SET and CH6SET are not available for the ADS1294. CH7SET and CH8SET registers are not available for the ADS1294 and
ADS1296.
(3)
The RLD_SENSP, PACE_SENSP, LOFF_SENSP, LOFF_SENSN, and LOFF_FLIP registers bits[5:4] are not available for the
ADS1294. Bits[7:6] are not available for the ADS1294/6.
38
Copyright 2010, Texas Instruments Incorporated
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