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参数资料
| 型号： | PADS1298CZXGT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封装： | 8 X 8 MM, LEAD FREE, PLASTIC, NFBGA-64 |
| 文件页数： | 38/73页 |
| 文件大小： | 957K |
| 代理商： | PADS1298CZXGT |
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PRODUCTPREVIEW
www.ti.com
SBAS459C – JANUARY 2010 – REVISED MARCH 2010
CHnSET: Individual Channel Settings (n = 1 : 8)
Address = 05h to 0Ch
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PD
GAIN2
GAIN1
GAIN0
0
MUXn2
MUXn1
MUXn0
The CH[1:8]SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See
the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective
channels.
Bit [7]
PD: Power-down
This bit determines the channel power mode for the corresponding channel.
0 = Normal operation (default)
1 = Channel power-down
Bits [6:4]
GAIN[2:0]: PGA gain
These bits determine the PGA gain setting.
000 = 6 (default)
001 = 1
010 = 2
011 = 3
100 = 4
101 = 8
110 = 12
Bit [3]
Always write '0'
Bits [2:0]
MUXn[2:0]: Channel input
These bits determine the channel input selection.
000 = Normal electrode input (default)
001 = Input shorted (for offset or noise measurements)
010 = Used in conjunction with RLD_MEAS bit for RLD measurements. See the Right Leg Drive (RLD DC Bias Circuit)
subsection of the ECG-Specific Functions section for more details.
011 = MVDD for supply measurement
100 = Temperature sensor
101 = Test signal
110 = RLD_DRP (positive electrode is the driver)
111 = RLD_DRN (negative electrode is the driver)
RLD_SENSP
Address = 0Dh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RLD8P
RLD7P
RLD6P
RLD5P
RLD4P
RLD3P
RLD2P
RLD1P
This register controls the selection of the positive signals from each channel for right leg drive derivation. See the
Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details.
Note that registers bits[5:4] are not available for the ADS1294. Bits[7:6] are not available for the ADS1294/6.
RLD_SENSN
Address = 0Eh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RLD8N
RLD7N
RLD6N
RLD5N
RLD4N
RLD3N
RLD2N
RLD1N
This register controls the selection of the negative signals from each channel for right leg drive derivation. See
the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details.
Note that registers bits[5:4] are not available for the ADS1294. Bits[7:6] are not available for the ADS1294/6.
Copyright 2010, Texas Instruments Incorporated
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