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SBAS459C – JANUARY 2010 – REVISED MARCH 2010
User Register Description
ID: ID Control Register (Factory-Programmed, Read-Only)
Address = 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REV_ID3
REV_ID2
REV_ID1
N/A
DEV_ID2
DEV_ID1
NU_CH2
NU_CH1
The ID Control Register is programmed during device manufacture to indicate device characteristics.
Bits [7:3]
N/A
Bits [2:0]
Factory-programmed device identification bits (read-only)
These bits indicate the device version.
000 = ADS1294; 24-bit resolution, 4 channels
001 = ADS1296; 24-bit resolution, 6 channels
010 = ADS1298; 24-bit resolution, 8 channels
011 = Reserved for future use
100 = Reserved for future use
101 = Reserved for future use
110 = Reserved for future use
111 = Reserved for future use
CONFIG1: Configuration Register 1
Address = 01h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HR
DAISY_EN
CLK_EN
0
DR2
DR1
DR0
Bit [7]
HR: High-Resolution/Low-Power mode
This bit determines whether the device runs in Low-Power or High-Resolution mode.
0 = Low-Power mode (default)
1 = High-Resolution mode
Bit [6]
DAISY_EN: Daisy-chain/multiple readback mode
This bit determines which mode is enabled.
0 = Daisy-chain mode (default)
1 = Multiple readback mode
Bit [5]
CLK_EN: CLK connection(1)
This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bits [4:3]
Must always be set to '0'
Bits [2:0]
DR[2:0]: Output data rate.
For high resolution mode, fMOD = fCLK/4. For low power mode, fMOD = fCLK/8.
These bits determine the output data rate of the device.
(1)
Additional power will be consumed when driving external devices.
BIT
DATA RATE
HIGH-RESOLUTION MODE(1)
LOW-POWER MODE(2)
000
fMOD/16
32kSPS
16kSPS
001
fMOD/32
16kSPS
8kSPS
010
fMOD/64
8kSPS
4kSPS
011
fMOD/128
4kSPS
2kSPS
100
fMOD/256
2kSPS
1kSPS
101
fMOD/512
1kSPS
500SPS
110 (default)
fMOD/1024
500SPS
250SPS
111
DO NOT USE
N/A
(1)
Additional power will be consumed when driving external devices.
(2)
fCLK = 2.048MHz.
Copyright 2010, Texas Instruments Incorporated
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