Analog Integrated Circuit Device Data
36
Freescale Semiconductor
13892
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages.
GNDREG3
Ground for regulators 3.
GPO1
General purpose output 1. Intended to be used for battery
thermistor biasing. In this case, connect a 10 K
Ω resistor
from GPO1 to ADIN5, and one from ADIN5 to GND.
GPO2
General purpose output 2.
GPO3
General purpose output 3.
GPO4
General purpose output 4. It can be configured for a
muxed connection into Channel 7 of the GP ADC.
CONTROL LOGIC
LICELL
Coin cell supply input and charger output. The LICELL pin
provides a connection for a coin cell backup battery or
supercap. If the main battery is deeply discharged, removed,
or contact-bounced (i.e., during a power cut), the RTC
system and coin cell maintained logic will switch over to the
LICELL for backup power. This pin also works as a current-
limited voltage source for battery charging. A small capacitor
should be placed from LICELL to ground under all
circumstances.
XTAL1
32.768 kHz Oscillator crystal connection 1.
XTAL2
32.768 kHz Oscillator crystal connection 2.
GNDRTC
Ground for the RTC block.
CLK32K
32 kHz Clock output for peripherals. At system start-up,
the 32 kHz clock is driven to CLK32K (provided as a
peripheral clock reference), which is referenced to SPIVCC.
The CLK32K is restricted to state machine activation in
normal on mode.
CLK32KMCU
32 kHz Clock output for processor. At system start-up, the
32 kHz clock is driven to CLK32KMCU (intended as the CKIL
input to the system processor) referenced to VSRTC. The
driver is enabled by the start-up sequencer and the
CLK32KMCU is programmable for Low Power Off mode
control by the state machine.
RESETB AND RESETBMCU
Reset output for peripherals and processor respectively.
These depend on the Power Control Modes of operation
(Seeas reset for the processor, or peripherals in a power up
condition, or to keep one in reset while the other is up and
running.
WDI
Watchdog input. This pin must be high to stay in the On
mode. The WDI IO supply voltage is referenced to SPIVCC
(normally connected to SW4=1.8 V). SPIVCC must therefore
remain enabled to allow for proper WDI detection. If WDI
goes low, the system will transition to the Off state or Cold
Start (depending on the configuration).
STANDBY AND STANDBYSEC
Standby input signal from processor and from peripherals
respectively.
To ensure that shared resources are properly powered
when required, the system will only be allowed into Standby
when both the application processor (which typically controls
the STANDBY pin) and peripherals (which typically control
the STANDBYSEC pin) allow it. This is referred to as a
Standby event.
The Standby pins are programmable for Active High or
Active Low polarity, and that decoding of a Standby event will
take into account the programmed input polarities associated
with each pin. Since the Standby pin activity is driven
asynchronously to the system, a finite time is required for the
internal logic to qualify and respond to the pin level changes.