- 您现在的位置：买卖IC网 > PDF目录98050 > PC13892AJVK (FREESCALE SEMICONDUCTOR INC) 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 PDF资料下载
参数资料
| 型号： | PC13892AJVK |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MO-195AD, MABGA-139 |
| 文件页数： | 57/67页 |
| 文件大小： | 2571K |
| 代理商： | PC13892AJVK |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页当前第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页
Analog Integrated Circuit Device Data
60
Freescale Semiconductor
13892
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages.
RESETB is kept low and RESETBMCU is kept high.
CLK32KMCU is kept active if CLK32KMCU was set. The
reset timer starts running when entering Warm Start. When
expired, the Warm Start state is exited for the Watchdog
state, a WARMI interrupt is generated, and RESETB will go
high.
INTERNAL MEMHOLD POWER CUT
Power Cut description: When the supply at BP drops
below the UVDET threshold due to battery bounce or battery
removal, the Internal MemHold Power Cut mode is entered
and a Power Cut (PCUT) timer starts running. The backup
coin cell will now supply the RTC as well as the on chip
memory registers and some other power control related bits.
All other supplies will be disabled.
Internal MemHold Power Cut: As previously described, a
momentary power interruption will put the system into the
Internal MemHold Power Cut state if PCUTs are enabled.
The backup coin cell will now supply 13892’s core along with
the 32 k crystal oscillator, the RTC system and coin cell
backed up registers. All regulators and switchers will be shut
down to preserve the coin cell and RTC as long as possible.
Both RESETB and RESETBMCU are tripped, bringing the
entire system down along with the supplies and external
clock drivers, so the only recovery out of a Power Cut state is
to reestablish power and initiate a Cold Start.
POWER SAVING
SYSTEM STANDBY
A product may be designed to go into DSM after periods of
inactivity, such as if a music player completes a play list and
no further activity is detected, or if a gaming interface sits idle
for an extended period. Two Standby pins are provided for
board level control of timing in and out of such deep sleep
modes.
When a product is in DSM it may be able to reduce the
overall platform current by lowering the switcher output
voltage, disabling some regulators, or forcing GPOx low. This
can be obtained by SPI configuration of the Standby
response of the circuits along with control of the Standby
pins.
To ensure that shared resources are properly powered
when required, the system will only be allowed into Standby
when both the application processor (which typically controls
the STANDBY pin) and peripherals (which typically control
the STANDBYSEC pin) allow it—this is referred to as a
Standby event.
REGULATOR MODE CONTROL
The regulators with embedded pass devices (VDIG, VPLL,
VIOHI, VUSB, VUSB2, and VAUDIO) operate in two modes:
a normal mode, and a low power mode. The transition
between both modes occurs automatically, based on the load
current. Therefore, no specific control is required to put these
regulators in a low power mode (i.e., “On” implies an adaptive
mode control” based on load current). Bits are reserved in
case the automatic scheme shows to be insufficient.
The regulators with external pass devices (VSD, VVIDEO,
VGEN1, and VGEN2) can also operate in a normal and low
power mode. However, since a load current detection cannot
be performed for these regulators, the transition between
both modes is not automatic, and is controlled by setting the
corresponding mode bits for the operational behavior
desired.
The regulators VGEN3, and VCAM can be configured for
using the internal pass device or external pass device as
explained in LDOs on page 48. Therefore, depending on the
configuration selected, the automatic low power mode is or is
not available.
BUCK SWITCHERS
Operational modes of the Buck switchers can be
controlled by direct SPI programming, altered by the state of
the STANDBY pins, by direct state machine influence (i.e.,
entering Off or low power Off states, for example), or by load
current magnitude when so configured. Available modes
include PWM with No Pulse Skipping (PWM), PWM with
Pulse Skipping (PWMPS), Pulse Frequency Mode (PFM),
and Off. The transition between the two modes PWMPS and
PFM can occur automatically based on the load current
(auto). Therefore, no specific control is required to put the
switchers in a low power mode. When the buck switchers are
not configured in the auto mode, power savings may be
achieved by disabling the switchers when not needed, or
running them in PFM mode, if loading conditions are light
enough.
SW1, SW2, SW3, and SW4 can be configured for mode
switching with STANDBY or autonomously, based on load
current with adaptive mode control (Auto). Additionally,
provisions are made for maintaining PFM operation in
USEROFF and MEMHOLD modes, to support state retention
for faster startup from the low power Off modes, for Warm
Start or Warm Boot.
POWER GATING SYSTEM
The low power Off states are provided to allow faster
system booting from two pseudo Off conditions: Memory
Hold, which keeps external memory powered for self refresh,
and User Off, which keeps the processor powered up for
state retention. For reduced current drain in low power Off
states, parts of the system can benefit from power gating, to
isolate the minimum essentials for such operational modes. It
is also necessary to ensure that the power budget on backed
up domains is within the capabilities of switchers in PFM
mode. An additional benefit of power gating peripheral loads
during system startup is to enable the processor core to
complete booting and begin running software before
additional supplies or peripheral devices are powered. This
allows system software to bring up the additional supplies
and close power gating switches in the most optimum order
相关PDF资料 |
PDF描述 |
|---|---|
| PC13892BJVL | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| PC13892BJVLR2 | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| PC14568ED/R2 | SPECIALTY ANALOG CIRCUIT, PDIP16 |
| PC33099DW | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| PC33253DW | STEPPER MOTOR CONTROLLER, 2 A, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PC13892AJVKR2 | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Tape and Reel |
| PC13892AJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Bulk |
| PC13892AJVLR2 | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Tape and Reel |
| PC13892BJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Trays |
| PC13892JVK | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Bulk |
发布紧急采购，3分钟左右您将得到回复。