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参数资料
| 型号： | PC13892AJVK |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MO-195AD, MABGA-139 |
| 文件页数： | 39/67页 |
| 文件大小： | 2571K |
| 代理商： | PC13892AJVK |
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Analog Integrated Circuit Device Data
44
Freescale Semiconductor
13892
FUNCTIONAL DEVICE OPERATION
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages.
SPI INTERFACE
The IC contains a SPI interface port which allows access
by a processor to the register set. Via these registers, the
resources of the IC can be controlled. The registers also
provide status information about how the IC is operating as
well as information on external signals.
The SPI port utilizes 32-bit serial data words comprised of
1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits.
The addressable register map spans 64 registers of 24 data
bits each.
I2C INTERFACE
When configured for I2C mode, the interface may be used
to access the complete register map. Since SPI configuration
is more typical, references within this document will generally
refer to the common register set as a “SPI map” and bits as
“SPI bits”. However, it should be understood that access
reverts to I2C mode when configured as such.
The SPI pins CLK and MISO are reused for the SCL and
SDA lines respectively. Selection of I2C mode for the
interface is configured by hardwiring the CS pin to VCORE on
the application board.
Table 13. Muxed Pin Options for SPI and I2C Interfaces (I2C Functions)
PIN NAME
I2C Mode Functionality
CS
Configuration(38)
CLK
SCL: I2CBUS clock
MISO
SDA: Bi-directional serial data line
MOSI
A0 Address Selection(39)
Notes
38.
CS tied to VCORE at Cold Start configures interface for I2C mode; the pin is not used in I2C mode other than for configuration.
39.
In I2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses.
The I2C mode of the interface is implemented generally
following the Fast Mode definition, which supports up to
400 kbits/s operation. (exceptions to the standard are noted
to be 7-bit only addressing and no support for General Call
addressing).
Timing diagrams, electrical specifications, and further
details can be found in the I2C specification, which is
available for download at:
INTERRUPT CONTROL
The system is informed about important events based on
interrupts. Unmasked interrupt events are signaled to the
processor by driving the INT pin high; this is true whether the
communication interface is configured for SPI or I2C.
Each interrupt is latched so that even if the interrupt source
becomes inactive, the interrupt will remain set until cleared.
Each interrupt can be cleared by writing a 1 to the appropriate
bit in the Interrupt Status register. This will also cause the
interrupt line to go low. If a new interrupt occurs while the
processor clears an existing interrupt bit, the interrupt line will
remain high.
Each interrupt can be masked by setting the
corresponding mask bit to a 1. As a result, when a masked
interrupt bit goes high, the interrupt line will not go high. A
masked interrupt can still be read from the Interrupt Status
register. This gives the processor the option of polling for
status from the IC. The IC powers up with all interrupts
masked, so the processor must initially poll the device to
determine if any interrupts are active. Alternatively, the
processor can unmask the interrupt bits of interest. If a
masked interrupt bit was already high, the interrupt line will go
high after unmasking.
Interrupts generated by external events are debounced;
therefore, the event needs to be stable throughout the
debounce period before an interrupt is generated. Nominal
debounce periods for each event are documented in the INT
summary table following later in this chapter. Due to the
asynchronous nature of the debounce timer the effective
debounce time can vary slightly.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PC13892AJVKR2 | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Tape and Reel |
| PC13892AJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Bulk |
| PC13892AJVLR2 | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Tape and Reel |
| PC13892BJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Trays |
| PC13892JVK | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Bulk |
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