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| 型号： | PC13892AJVK |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA139 |
| 封装： | 7 X 7 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MO-195AD, MABGA-139 |
| 文件页数： | 55/67页 |
| 文件大小： | 2571K |
| 代理商： | PC13892AJVK |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
59
13892
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages.
OPERATIONAL MODES
The following are text descriptions of the power states of
the system with additional details of the state machine to
complement Figure 13. Note that SPI control is only possible
in the Watchdog, On, and User Off Wait states, and that the
interrupt line INT is kept low in all states except for Watchdog
and On.
OFF
If the supply at BP is above the UVDET threshold, only the
IC core circuitry at VCOREDIG and the RTC module are
powered. All other supplies are inactive. To exit the Off mode,
a valid turn on event is required. No specific timer is running
in this mode.
If the supply at BP is below the UVDET threshold, no turn
on events are accepted. If a valid coincell is present, the core
gets its power from LICELL. The only active circuitry is the
RTC module, and the BP greater than UVDET detection.
COLD START
This is entered upon a Turn On event from Off, Warm
Boot, successful PCUT, or Silent System Restart. The first
8.0 ms are used for initialization which includes bias
generation, PUMS / configuration latching, and qualification
of the input supply level BP. The switchers and regulators are
then powered up sequentially to limit the inrush current. The
reset signals RESETB and RESETBMCU are kept low. The
Reset timer starts running when entering Cold Start. The
input control pins WDI and STANDBYx are ignored.
WATCHDOG
The system is fully powered and under SPI control.
RESETB and RESETBMCU are high. The Watchdog timer
starts running when entering the Watchdog state. When
expired, the system transitions to the On state, where WDI
will be checked and monitored. The input control pins WDI
and STANDBYx are ignored while in the Watchdog state.
ON
The system is fully powered and under SPI control.
RESETB and RESETBMCU are high. The WDI pin must be
high to stay in this mode.
USER OFF WAIT
The system is fully powered and under SPI control. The
WDI pin no longer has control over the part. The Wait mode
is entered by a processor request for User Off. The Wait timer
starts running when entering User Off Wait mode. This leaves
the processor time to suspend or terminate its tasks.
MEMORY HOLD AND USER OFF (LOW POWER
OFF STATES)
As noted in the User Off Wait description, the system is
directed into low power Off states, based on a SPI command
in response to an intentional Turn Off by the end user. The
only exit then will be a Turn On event.
To an end user, the Memory Hold and User Off states look
like the product has been shut down completely. However, a
faster startup is facilitated by maintaining external memory in
self-refresh mode (Memory Hold and User Off mode), as well
as powering portions of the processor core for state retention
(User Off only).
MEMORY HOLD
RESETB and RESETBMCU are low, and both CLK32K
and CLK32KMCU are disabled (CLK32KMCU active if DRM
is set).
Upon a Turn On event, the Cold Start state is entered, the
default power up values are loaded, and the MEMHLDI
interrupt bit is set. A Cold Start out of the Memory Hold state
will result in shorter boot times compared to starting out of the
Off state, since software does not have to be loaded and
expanded from flash. The startup out of Memory Hold is also
referred to as Warm Boot. No specific timer is running in this
mode.
USER OFF
RESETB is low and RESETBMCU is kept high. The
32 kHz peripheral clock driver CLK32K is disabled;
CLK32KMCU (connected to the processor’s CKIL input) is
maintained in this mode, if the CLK32KMCUEN and
USEROFFCLK bits are both set, or if DRM is set.
Any peripheral loading on SW1 and/or SW2 should be
isolated from the output node(s) by the PWGT1 switch, which
opens in both low power Off modes, due to the RESETB
transition. In this way, leakage is minimized from the power
domain, maintaining the processor core.
Since power is maintained for the core (which is put into its
lowest power state), and since MCU RESETBMCU does not
trip, the processor’s state may be quickly recovered when
exiting USEROFF upon a Turn On event. The CLK32KMCU
clock can be used for very low frequency / low power idling of
the core(s), minimizing battery drain while allowing a rapid
recovery from where the system left off before the USEROFF
command.
Upon a Turn On event, Warm Start state is entered, and
the default power up values are loaded. A Warm Start out of
User Off will result in an almost instantaneous startup of the
system, since the internal states of the processor were
preserved along with external memory. No specific timer is
running in this mode.
WARM START
Entered with a Turn On event from User Off. The first
8.0 ms is used for initialization which includes bias
generation, PUMS latching, and qualification of the input
supply level BP. The switches and regulators are then
powered up sequentially to limit the inrush current.
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相关代理商/技术参数 |
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|---|---|
| PC13892AJVKR2 | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Tape and Reel |
| PC13892AJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Bulk |
| PC13892AJVLR2 | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Tape and Reel |
| PC13892BJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Trays |
| PC13892JVK | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Bulk |
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