PEB 20550
PEF 20550
Operational Description
Semiconductor Group
116
01.96
Set EPIC-1 to normal mode
Write
OMDR = C0
H
Read
ISTA = 20
H
Read
ISTA_E = 08
H
Read
STAR_E = 25
H
Reset tristate field of Data Memory (DM)
Write
MADR = 00
H
Write
MACR = 68
H
Read
STAR
set EPIC-1 to CM-normal mode; Interrupt line will go active
EPIC-1 interrupt
PFI-interrupt: PCM-synchronisity status has changed
ELIC is synchronized to PCM-interface; MFIFO ready
all bits of time slot set to high impedance
write MADR to all locations of PCM-tristate field
Wait for STAR:MAC = 0
3.8.6.2 SACCO
-
A Initialization Example
Configure the SACCO-A for communication with downstream subscribers
Write
MODE = A8
H
set SACCO-B to transparent mode 1; switch receiver active
Write
RAH1 = 00
H
response SAPI1: Signaling data
Write
RAH2 = 40
H
response SAPI 2: Packet-switched data
(Write
CCR2 = 00
H
)
reset value: T
×
DA pin disabled; standard data sampling;
RFS-interrupt disabled
Write
CCR1 = 87
H
power-up SACCO-A in point to point configuration and clock
mode 3 with double rate clock; inter frame timefill = all ’1’s
Reset the SACCO-A’s FIFOs
Write
CMDR = C1
H
reset CPU accessible and CPU inaccessible part of RFIFO,
and reset XFIFO; the interrupt line will go active
Read
ISTA = 02
H
interrupt of SACCO-A
Read
ISTA_A = 10
H
transmit pool ready
3.8.6.3 D-Channel Arbiter Initialization Example
Enable D-channel transmission to CFI-port 0, channel 0
(Write
XDC = 00
H
)
reset value: broadcasting disabled; transmit to channel 0
of port 0
Enable D-channel reception on CFI-port 0, channel 0
Write
AMO = F9
H
start with maximum selection delay; suspend counter active;
control of D-channel to take place via C/I-bit; control
channel master enabled
Write
DCE0 = 01
H
enable CFI-port 0, channel 0 for data reception