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PEB 20550
PEF 20550
Detailed Register Description
Semiconductor Group
154
01.96
4.6.26
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: 0xxxxxxx
B
Signaling FIFO (CIFIFO)
read
read
address: 0C
H
address: 18
H
The 9 byte deep CIFIFO stores the addresses of CFI time slots in which a C/I- and/or a
SIG-value change has taken place. This address information can then be used to read
the actual C/I- or SIG-value from the control memory.
SBV
Signaling Byte Valid.
0…the SAD6..0 bits are invalid.
1…the SAD6..0 bits indicate a valid subscriber address. The polarity of SBV
is chosen such that the whole 8 bits of the CIFIFO can be copied to the
MAAR register in order to read the upstream C/I- or SIG-value from the
control memory.
SAD6..0
Subscriber Address bits 6..0; The CM-address which corresponds to the CFI
time slot where a C/I- or SIG-value change has taken place is encoded in
these bits. For C/I-channels SAD6..0 point to an even CM-address (C/
I-value), for SIG-channels SAD6..0 point to an odd CM-address (stable SIG-
value).
4.6.27
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: 00
H
Timer Register (TIMR)
write
write
address: 0C
H
address: 18
H
The EPIC-1 timer can be used for 3 different purposes: timer interrupt generation
(ISTA:TIG), FSC multiframe generation (CMD2:FC2..0 = 111) and last look period
generation.
SSR
Signaling Sampling Rate.
0… the last look period is defined by TVAL6..0.
1… the last look period is fixed to 125
μ
s.
bit 7
SBV
bit 0
SAD0
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
bit 7
SSR
bit 0
TVAL0
TVAL6
TVAL5
TVAL4
TVAL3
TVAL2
TVAL2