PEB 20550
PEF 20550
Detailed Register Description
Semiconductor Group
153
01.96
4.6.24
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: xx
H
MF-Channel Subscriber Address Register (MFSAR)
read/write
read/write
address: 0A
H
address: 14
H
The exchange of monitor data normally takes place with only one subscriber circuit at a
time. This register serves to point the MF-handler to that particular CFI time slot.
MFTC1..0
MF Channel Transfer Control 1..0; these bits, in addition to CMDR:MFT1,0
and OMDR:MFPS control the MF-channel transfer as indicated in
table 21
.
SAD5..0
Subscriber address 5..0; these bits define the addressed subscriber. The
CFI time slot encoding is similar to the one used for Control Memory
accesses using the MAAR-register (
tables 19
and
20
):
CFI time slot encoding of MFSAR derived from MAAR:
MAAR:MA7 selects between upstream and downstream CM-blocks. This information is
not required since the transfer direction is defined by CMDR (transmit or receive).
MAAR:MA0 selects between even and odd time slots. This information is also not
required since MF-channels are always located on even time slots.
4.6.25
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: empty
Monitor/Feature Control Channel FIFO (MFFIFO)
read/write
read/write
address: 0B
H
address: 16
H
The 16-byte bi-directional MFFIFO provides intermediate storage for data bytes to be
transmitted or received over the monitor or feature control channel.
MFD7..0
MF Data bits 7..0; MFD7 (MSB) is the first bit to be sent over the serial CFI,
MFD0 (LSB) the last.
Note: The byte n + 1 of an n-byte transmit message in monitor channel is not defined.
bit 7
MFTC1
bit 0
SAD0
MFTC0
SAD5
SAD4
SAD3
SAD2
SAD1
MAAR:
MA7
MA6
↓
SAD5
MA5
↓
SAD4
MA4
↓
SAD3
MA3
↓
SAD2
MA2
↓
SAD1
MA1
↓
SAD0
MA0
MFSAR: MFTC1
MFTC0
bit 7
MFD7
bit 0
MFD0
MFD6
MFD5
MFD4
MFD3
MFD2
MFD1