![](http://datasheet.mmic.net.cn/330000/PEF20550_datasheet_16444055/PEF20550_141.png)
PEB 20550
PEF 20550
Detailed Register Description
Semiconductor Group
141
01.96
4.6.9
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: FF
H
Configurable Interface Bit Number Register (CBNR)
read/write
read/write
address: 18
H
address: 30
H
CBN7..0
CFI-Bit Number 7..0.
The number of bits that constitute a CFI-frame must be programmed to
CMD2, CBNR:CBN9..0 as indicated below.
CBN9..0 = number of bits
1
For a 8-kHz frame structure, the number of bits per frame can be derived
from the data rate by division with 8000.
4.6.10
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: 00
H
Configurable Interface Time Slot Adjustment Register (CTAR)
read/write
read/write
address: 19
H
address: 32
H
TSN6..0
Time Slot Number.
The CFI-framing signal (PFS if CMD1:CSS = 0 or FSC if CMD1:CSS = 1)
marks the CFI time slot called TSN according to the following formula:
TSN6
..
0 = TSN + 2
E.g.: If the framing signal is to mark time slot 0 (bit 7), CTAR must be set to
02
H
(CBSR to 20
H
).
Note: If CMD1:CSS = 0, the CFI-frame will be shifted - together with the FSC-output
signal - with respect to PFS. The position of the CFI-frame relative to the
FSC-output signal is not affected by these settings, but is instead determined by
CMD2:FC2
..
0. If CMD1:CSS = 1, the CFI-frame will be shifted with respect to the
FSC-input signal.
bit 7
CBN7
bit 0
CBN0
CBN6
CBN5
CBN4
CBN3
CBN2
CBN1
bit 7
bit 0
TSN0
0
TSN6
TSN5
TSN4
TSN3
TSN2
TSN1