PEB 20550
PEF 20550
Functional Description
Semiconductor Group
41
01.96
2
Functional Description
2.1
The ELIC integrates the existing Siemens device PEB 2055 (EPIC-1), a two channel
HDLC-Controller (SACCO: Special Application Communication Controller) with a
PEB 2050 (PBC) compatible auto-mode, a D-channel arbiter, a configurable bus
interface and typical system glue logic into one chip. It covers all control functions on
digital and analog line cards and can be combined via IOM-2 interface with layer-1
circuits or special application devices (e.g. ADPCM/PCM-converters). Due to its flexible
bus interface it fits perfectly into Siemens / Intel or Motorola microprocessor
architectures.
General Functions and Device Architecture
2.2
Functional Blocks
2.2.1
All registers and the FIFOs of the ELIC are accessible via the flexible bus interface
supporting Siemens / Intel and Motorola type microprocessors. Depending on the
register functionality a read, write or read/write access is possible.
The bus interface consists of the following elements
Data bus, 8-bit wide, AD0-7, D0-7
Address bus, 8-bit wide, P0.0-0.7, A0-7
Two chip select lines, CSE and CSS
Address latch enable, ALE
Two read/write control lines, RD, DS and WR, R or W
Bus Interface
The ALE-line is used to control the bus structure and interface type.
Table 1
Selectable Bus Configurations
ALE
Fixed to
V
DD
Fixed to ground
Switching
Interface
Motorola
Siemens / Intel
Siemens / Intel
Bus Structure
demultiplexed
demultiplexed
multiplexed
Pin 9
DS
RD
RD
Pin 8
R or W
WR
WR