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PEB 20550
PEF 20550
Functional Description
Semiconductor Group
58
01.96
RME-interrupt is generated. The configuration of the RFIFO prior to and after
acknowledgment is shown in
figure 32
(
left
). If frames longer than 64 bytes are
received, the SACCO will repeatedly prompt to read out 32-byte data blocks via interrupt
or DMA.
Figure 32
Frame Storage in RFIFO (single frame / multiple frames)
In the case of
several shorter frames
, up to 17 frames may be stored in the RFIFO.
Nevertheless, only one frame is stored in the CPU accessible part of the RFIFO. E.g., if
frame i (or the last part of frame i) is stored in the accessible RFIFO-part, up to 16 short
frames may be stored in the other half (i + 1, i + 2, …, i + n, n
≤
16). This behavior is
illustrated in
figure 32
(
right
).
Note: After every frame a receive status byte is appended, specifying the status of the
frame (e.g. if the CRC-check is o.k.).
When using the DMA-mode, the SACCO requests fixed size block transfers (4, 8, 16 or
32 bytes). The valid byte count is determined by reading the registers RBCH, RBCL
following the RME-interrupt.
Transmit FIFO
The transmit FIFO (XFIFO) provides a 2
×
32 bytes capability to intermediately store
transmit data.
In interrupt mode the user loads the data and then executes a transmit command.
When the frames are longer than 32 bytes, a XPR-interrupt is issued as soon as the
accessible XFIFO-part is available again.
ITD05830
Block B+1
Block B+1
Frame j
Free
Free
Free
Frame i+n
Free
Last Block of
Frame i
Free
Free
CPU Inaccessible
FIFO Part,
32 Bytes
0 < n < 17
RFIFO Status Prior
to Acknowledgement
RFIFO Status After
Acknowledgement
to Acknowledgement
Acknowledgement
Free
32 Bytes
FIFO Part,
CPU Accessible
32 Bytes
Frame j
Block B
RFIFO Status Prior
RFIFO Status After
Frame i+1
Frame i+n
Frame i+2
Frame i+1