![](http://datasheet.mmic.net.cn/330000/PEF20550_datasheet_16444055/PEF20550_155.png)
PEB 20550
PEF 20550
Detailed Register Description
Semiconductor Group
155
01.96
TVAL6..0
Timer Value bits 6..0; the timer period, equal to (1+TVAL6..0)
×
250
μ
s, is
programmed here. It can thus be adjusted within the range of 250
μ
s up to
32 ms.
The timer is started as soon as CMDR:ST is set to 1 and stopped by writing the
TIMR-register or by selecting OMDR:OMS0 = 0.
4.6.28
Access in demultiplexed
μ
P-interface mode:
Access in multiplexed
μ
P-interface mode:
Reset value: 05
H
Status Register EPIC
-1 (STAR_E)
read
read
address: 0D
H
address: 1A
H
The status register STAR displays the current state of certain events within the EPIC-1.
The STAR register bits do not generate interrupts and are not modified by reading
STAR.
MAC
Memory Access
0…no memory access is in operation.
1…a memory access is in operation. Hence, the memory access registers
may not be used.
Note: MAC is also set and reset during synchronous transfers.
TAC
Timer Active
0…the timer is stopped.
1…the timer is running.
PCM-Synchronization Status.
1…the PCM-interface is synchronized.
0…the PCM-interface is not synchronized. There is a mismatch between the
PBNR-value and the applied clock and framing signals (PDC/PFS) or
OMDR:OMS0 = 0.
MF-Channel Transfer in Operation.
0…no MF-channel transfer is in operation.
1…an MF-channel transfer is in operation.
MF-Channel Transfer Aborted.
0…the remote receiver did not abort a handshake message transfer.
1…the remote receiver aborted a handshake message transfer.
MFFIFO-Access Enable.
0…the MFFIFO may not be accessed.
1…the MFFIFO may be either read or written to.
PSS
MFTO
MFAB
MFAE
bit 7
MAC
bit 0
MFFE
TAC
PSS
MFTO
MFAB
MFAE
MFRW