PEB 20550
PEF 20550
Functional Description
Semiconductor Group
57
01.96
For further information refer to
chapter 3.6.2
(
Data Transmission in DMA-Mode
) and
chapter 3.6.4
(
Data Reception in DMA-Mode
).
Figure 31
DMA-Transfers with Pulsed DACK (read or write)
If a pulsed DACK-signal is used the DRQR/DRQT-signal will be deactivated with the
rising edge of RD/WR-operation (n-1) but activated again with the following rising edge
of DACK. With the next falling edge of DACK (DACK ‘n’) it will be deactivated again (see
figure 31
).
This behavior might cause a short negative pulse on the DRQR/DRQT-line depending
on the timing of DACK vs. RD/WR.
2.2.7.3 FIFO-Structure
Two independent 64-byte deep FIFOs for transmit and receive direction are provided.
They enable an intermediate storage of data between the serial and the parallel (CPU)
interface. The FIFOs are divided into two halves of 32 bytes each, where only one half
is accessible by the CPU- or DMA-controller.
Receive FIFO
The receive FIFO (RFIFO) is organized in two parts of 32 bytes each, of which only one
part is accessible for the CPU.
When a frame with
up to 64 bytes
is received, the complete frame may be stored in
RFIFO. After the first 32 bytes have been received, the SACCO prompts to read the data
block by means of interrupt or DMA-request (RPF-interrupt or activation of DRQR-line).
The data block remains in the RFIFO until a confirmation is given to the SACCO-
acknowledging the reception of the data. This confirmation is either a RMC- (Receive
Message Complete) command in interrupt mode or it is implicitly achieved in DMA-mode
after 32 bytes have been read. As a result it is possible in interrupt mode to read out the
data block any number of times until the RMC-command is executed. Upon the
confirmation the second data block is shifted into the accessible RFIFO-part and an
DRQR / DRQT
DACK
WR / RD
n
n-1
n-2
ITD06896